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| SH77722 (SH-NaviJ2) Specifications0 o6 x. R8 N% ], N" k* y. h
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Type name
* o0 ?1 ~: @. z( d/ X | R8A77722DA01BGV
( G4 r( L: B* w2 {: j' B | R8A77722DA02BGV0 T* Y6 f) \- N! k1 p, o$ b
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Power supply voltage9 [6 V- c- G, _, K2 Z+ b* m
| 1.15 to 1.3 V (internal),
% w% a2 }3 J) }& P8 u3.3 V and 1.8 V (external)
8 m( |8 e1 Z5 t- b1 Q) Q$ b* c3 n X | 1.2 to 1.35 V (internal), 2 `5 g3 ^7 s1 b% ]5 c: Q3 n) `. s
3.3 V and 1.8 V (external)
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Maximum operating frequency: I- a7 r% c# @7 t
| 336 MHz' Z6 N- s. Z6 v9 l1 p6 E% |* o
| 400 MHz+ J" v% g# b" K. k' U
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Processing performance/ ~# J& }( r6 l% ]& R( N* |
| 600MIPS, 2.3GFLOPS
3 @ z# e. o% G e0 r$ r6 S | 720MIPS, 2.8GFLOPS
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CPU core
: E2 Q8 O% p# G, J' _. T1 N6 t | SH-4A core1 A! R! y' L( N/ F4 A1 r
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On-chip RAM
, r F: ~9 [8 B: S. ^6 |4 b9 { | ILRAM: 16 Kbytes
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Cache memory
- |# h2 E$ L& R* M | 4-way set associative type with separate 32 Kbytes for instructions and 32 Kbytes for data
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External memory- _1 W' _; |- z# S6 Y q9 s
| DDR2-SDRAM (data transfer rate: 336 MHz) directly connectable to dedicated DDR2 bus
0 y+ `8 r/ T( I5 ^6 Z | DDR2-SDRAM (data transfer rate: 266 MHz) directly connectable to dedicated DDR2 bus$ F/ C3 s1 }2 @5 @3 ?4 C: }9 N2 V
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SRAM or ROM directly connected to extension bus
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Extension bus) e W- N+ b2 W4 n0 ?8 ^1 z: k
| Address space: 64 Mbytes × 3
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Main on-chip peripheral functions
; x3 J- l& ~8 a4 ? | Renesas Graphics processor(2D/3D)
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Display control: outputs for two screens (digital RGB and LVDS)
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Video input interface+ I$ Q2 C( e. O" E
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SD card host interface × 2 channels% e! [; M6 T2 I
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USB 2.0 host/function interface6 b: R6 H+ X2 L. N* ]1 I
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FM multiplex decoder
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Controller area network (RCAN) interface × 2 channels+ P" F$ X& G! A4 \! y
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MOST interface module
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Various audio interfaces × 4 channels
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Dedicated DMAC × 26 channels
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I2C bus interface × 2 channels/ v& [; y+ N( J) k! X* A+ T
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Serial communication interface (SCIF) × 8 channels4 u8 K4 Y V5 r- j. j: t& B
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Remote control interface × 1 channel% F0 T4 @( D4 v9 L6 w% l
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A/D converter (10-bit) × 4 channels
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Timer × 9 channels. n1 g: k7 s0 ^& x7 P. K( u4 J+ ^
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On-chip debugging function w8 @0 c( Y" @: O
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Interrupt controller (INTC)
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Clock pulse generator (CPG): built-in PLL frequency multiplier
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Power-down modes
; K: ]. A. M2 r c+ h | Sleep mode" H) A) b( J R6 l+ v# e5 J( ]$ b
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Module standby mode4 v8 N: s+ F3 t) O& h. k# \
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DDR-SDRAM power supply backup mode3 l+ R* n9 I9 M: `. `8 L1 q
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Package
" c, ?8 h1 m# l/ C1 {* C | 449-pin BGA (21 mm × 21 mm)" f$ K+ i$ M& m# {( ?' z
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