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| SH77722 (SH-NaviJ2) Specifications
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Type name
* \; r5 |# _" I8 Q7 n1 } | R8A77722DA01BGV# V) O9 |4 ]6 i6 X) e- F( ~3 d) a* Y3 N! N
| R8A77722DA02BGV
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Power supply voltage
! P6 g( V4 c* | | 1.15 to 1.3 V (internal), 4 ?1 `4 [, i4 c. @1 ^6 M: ~
3.3 V and 1.8 V (external)) b0 V! W: p, h K
| 1.2 to 1.35 V (internal), 1 {/ a4 @, }0 z+ l9 I/ i
3.3 V and 1.8 V (external)
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Maximum operating frequency0 z* X, _2 d% _8 e3 R: C
| 336 MHz
$ E% x( |$ f9 Y | 400 MHz4 c% w# x1 Z* K A( W+ T e
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Processing performance
t( U$ i) z& G; ]) C | 600MIPS, 2.3GFLOPS
" P7 W {0 a5 X; m& i6 [ | 720MIPS, 2.8GFLOPS: g0 \& j1 c% B: l; e& ?6 C" I4 |6 Z
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CPU core
8 Y# O! a& i2 C | SH-4A core
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On-chip RAM
j# y& `! Y* r5 E+ { | ILRAM: 16 Kbytes, P* F, [0 t l/ ]* g9 P4 X) ?8 o
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Cache memory
( M9 z. u) c# ~- s! W6 M | 4-way set associative type with separate 32 Kbytes for instructions and 32 Kbytes for data
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External memory3 @& h. a8 d5 I$ o# e7 ^# F
| DDR2-SDRAM (data transfer rate: 336 MHz) directly connectable to dedicated DDR2 bus
8 U: x) u/ q: D9 p9 r/ r | DDR2-SDRAM (data transfer rate: 266 MHz) directly connectable to dedicated DDR2 bus# s Q" W3 z$ Y1 N/ E8 c' v, x
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SRAM or ROM directly connected to extension bus
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Extension bus$ F% G V, c. O9 h1 a* j
| Address space: 64 Mbytes × 3
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Main on-chip peripheral functions3 F8 p, o* W4 l7 {
| Renesas Graphics processor(2D/3D), `( ?# W) z& O
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Display control: outputs for two screens (digital RGB and LVDS)/ O& z. ]! T% P, R( O- \! S. k, V
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Video input interface$ }' l! k+ ^5 o7 r2 [$ A9 v
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SD card host interface × 2 channels
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USB 2.0 host/function interface& [2 M. _% t+ D' S0 j
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FM multiplex decoder1 h; k6 {- o6 G( ]
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Controller area network (RCAN) interface × 2 channels, \( g7 [) B. E6 H
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MOST interface module
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Various audio interfaces × 4 channels" m2 T/ q$ r% g) T9 y7 r$ C4 K
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Dedicated DMAC × 26 channels
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I2C bus interface × 2 channels
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Serial communication interface (SCIF) × 8 channels$ `5 `. i. K3 ]
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Remote control interface × 1 channel" U1 d' d9 j8 \/ o2 O9 E
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A/D converter (10-bit) × 4 channels. o }) s" n ^* o; J
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Timer × 9 channels
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On-chip debugging function
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Interrupt controller (INTC)
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Clock pulse generator (CPG): built-in PLL frequency multiplier
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Power-down modes5 R5 l2 L/ a* O+ x3 K4 Z/ A
| Sleep mode
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Module standby mode/ ?2 t% l: Q. K
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DDR-SDRAM power supply backup mode4 t$ k* H2 z( c: v' t' T5 G$ q7 N
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Package
7 X2 I. t5 m1 D F/ [: P' d2 h; N0 D5 G | 449-pin BGA (21 mm × 21 mm)# Z- g, w; ~$ E
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