Item
- D) F1 {2 A+ A9 ]! H- J | SH77722 (SH-NaviJ2) Specifications8 S0 }4 s. _8 `
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Type name0 I: X4 j$ _: ^6 n
| R8A77722DA01BGV
, ~4 Q' k* K% m1 ^2 [+ ? | R8A77722DA02BGV* Y! W4 Z, F( n* \. R
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Power supply voltage+ K% @0 u! X# Z W, R2 M n
| 1.15 to 1.3 V (internal), t) Y7 F: q% L! X; Y1 m. w4 E
3.3 V and 1.8 V (external)6 F1 A" r* k& @$ v; e8 Q* ?- @$ O5 b
| 1.2 to 1.35 V (internal),
1 S& s; i ^. p- r# ?& M; ^! w3.3 V and 1.8 V (external). P. b+ b& r' n7 C: E! t
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Maximum operating frequency
6 k; Q$ E5 p _) r: H | 336 MHz( ^ N- g+ \+ W" l# H
| 400 MHz3 ]5 r+ P+ z5 [) ]. X S
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Processing performance
& G# A! i( V( ? | 600MIPS, 2.3GFLOPS
: y2 [( w o& l# w6 p& h5 o | 720MIPS, 2.8GFLOPS5 P4 {' `4 P1 m) e
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CPU core% q4 [) c8 u1 M, r4 i9 z9 W$ `" `
| SH-4A core) I% r+ e8 `1 W- r3 f3 @
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On-chip RAM
7 t' n8 _/ H1 B# ~ | ILRAM: 16 Kbytes: X A- @8 E5 F1 T2 z9 ~
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Cache memory
2 u3 C; H: D6 Y5 z% {) `, f | 4-way set associative type with separate 32 Kbytes for instructions and 32 Kbytes for data
5 b7 b7 B! V/ b" z6 n* P |
External memory
/ u/ _' Q7 V1 I$ G6 K+ J | DDR2-SDRAM (data transfer rate: 336 MHz) directly connectable to dedicated DDR2 bus! }0 s! o; c/ K
| DDR2-SDRAM (data transfer rate: 266 MHz) directly connectable to dedicated DDR2 bus) ~# y; w4 [6 L% y
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SRAM or ROM directly connected to extension bus
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Extension bus
) Y$ {( E' N' U( V' h& t! Z | Address space: 64 Mbytes × 3: \5 P$ r1 B0 `: |/ Q# n$ I
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Main on-chip peripheral functions b' M" s1 M- C& H8 G7 q
| Renesas Graphics processor(2D/3D)+ S* N, ^$ a. e! f1 } |& {
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Display control: outputs for two screens (digital RGB and LVDS)8 K( }. } F6 k3 B1 G+ ]
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Video input interface9 V6 o5 }# A0 B& c5 O4 z# T7 f/ s: ^
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SD card host interface × 2 channels
9 u- V$ N9 g. b3 X7 R) G |
USB 2.0 host/function interface* c9 X3 L' \7 _4 H! x8 T
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FM multiplex decoder
1 _. Z M- @, i$ r* b& f( _$ b |
Controller area network (RCAN) interface × 2 channels
: ]9 Y7 W/ q; \0 ~6 t |
MOST interface module
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Various audio interfaces × 4 channels
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Dedicated DMAC × 26 channels
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I2C bus interface × 2 channels7 ^4 n7 f- Z/ r* d5 D
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Serial communication interface (SCIF) × 8 channels
: S3 G3 I9 ]2 L d& d$ R |
Remote control interface × 1 channel
1 P7 {$ Z$ n' [. w, d$ a |
A/D converter (10-bit) × 4 channels
- O" q m7 x4 Q# F+ T$ w* J' f' K3 V |
Timer × 9 channels; ]3 o4 _# r) j9 k6 p2 b9 U: m
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On-chip debugging function
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Interrupt controller (INTC)" W- p# Z$ A0 Y
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Clock pulse generator (CPG): built-in PLL frequency multiplier& j: M+ `6 t& O+ r' x; h; A6 U
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Power-down modes) |; @0 O5 U8 k K3 d8 U
| Sleep mode# L4 m) ^: ~2 ~3 D& w4 S* Z
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Module standby mode
+ t4 K$ F4 P. s& D |
DDR-SDRAM power supply backup mode
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Package
- y- u# d+ f8 a1 X | 449-pin BGA (21 mm × 21 mm)! ]% B/ g% g$ V% D
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