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Layout Guidelines for Optimized ESD Protection Diodes
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Karan Bhatia and Elyse Rosenbaum& N. B6 [. `& C9 Y( o" `
Department of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign* ? a9 k* d Y) i+ I, |) l; \
1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu
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6 b6 Z; v( d" D8 t0 iAbstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are2 g! g' U6 r, P- ]
investigated. The current compression point (ICP) is introduced to define the maximum current handling; P+ l7 {+ x$ Z# a- E6 L4 x( ?
capability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the! l* z; y! b+ p- K' ~
performance of the structures investigated herein. |
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