Item. V0 a! G$ |0 t0 H/ Q
| SH77722 (SH-NaviJ2) Specifications9 N+ K3 O% }9 T: a A% c9 o+ h& k5 G
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Type name1 y4 z' O# T5 |+ d0 {# e
| R8A77722DA01BGV
4 A4 ?- @( N; c l4 F# V% ^ | R8A77722DA02BGV% F! k( t$ y, |8 g
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Power supply voltage
0 K1 T* [- {* K7 Z5 M' z | 1.15 to 1.3 V (internal), 1 v- k' ^1 T; c2 X2 U! ^ G
3.3 V and 1.8 V (external)
: q9 A) t' [5 H# m( m& W" m | 1.2 to 1.35 V (internal), / }, y6 l: x/ c7 N) h1 F
3.3 V and 1.8 V (external)
3 o/ g2 {) F7 l5 n" {5 ~ |
Maximum operating frequency; x. o! f9 J( j: T0 R; A
| 336 MHz
( I; k) a ?- N/ o" x0 \ | 400 MHz& R8 \6 ]" [* W; L
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Processing performance* u/ t( a) l; z- d# Q* i. `
| 600MIPS, 2.3GFLOPS
& m3 S0 Z5 S$ Z" B | 720MIPS, 2.8GFLOPS! k4 w/ u2 F3 m
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CPU core
. `! P% Q0 ?; A | SH-4A core9 u6 I3 B# q- ^# }! J9 ~
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On-chip RAM/ Z, ~( X- D: B$ c" h0 L
| ILRAM: 16 Kbytes: N. ]: q1 I/ O. x7 U
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Cache memory
! b9 l* i" W# f; h4 H2 W2 E8 _ | 4-way set associative type with separate 32 Kbytes for instructions and 32 Kbytes for data$ U$ v$ {+ p* I" j9 [' t/ V
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External memory$ a5 s4 b* g+ a N) l
| DDR2-SDRAM (data transfer rate: 336 MHz) directly connectable to dedicated DDR2 bus6 F9 s5 w- p: ]2 E8 p% U/ k7 x# x
| DDR2-SDRAM (data transfer rate: 266 MHz) directly connectable to dedicated DDR2 bus0 n3 H# }8 P$ R" ~/ }7 a
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SRAM or ROM directly connected to extension bus
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Extension bus
* m0 m' A: w/ |7 x | Address space: 64 Mbytes × 3
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Main on-chip peripheral functions: r; M7 D! o0 @9 X7 u( u
| Renesas Graphics processor(2D/3D)
4 T4 P+ M4 R# _ f8 f4 h |
Display control: outputs for two screens (digital RGB and LVDS)
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Video input interface) `1 \$ ~! P a/ } ]! y7 b Q
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SD card host interface × 2 channels3 W% f. o, i; d1 P
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USB 2.0 host/function interface
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FM multiplex decoder
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Controller area network (RCAN) interface × 2 channels3 h+ a% G5 v4 O0 [2 _" u; v4 f
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MOST interface module, w" N* F% P1 _/ @. h1 w+ a
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Various audio interfaces × 4 channels
( u% }$ ]5 `3 Z+ r+ {7 | |
Dedicated DMAC × 26 channels0 M& {& W& }4 @, ?
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I2C bus interface × 2 channels. t4 M! ?& f8 X8 p! i, ^
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Serial communication interface (SCIF) × 8 channels
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Remote control interface × 1 channel
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A/D converter (10-bit) × 4 channels. S5 c( O; V) j. k$ X% N7 h
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Timer × 9 channels6 j+ K$ `5 I9 z# C
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On-chip debugging function
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Interrupt controller (INTC)
# B. x5 W [) ^" o+ L$ i$ E |
Clock pulse generator (CPG): built-in PLL frequency multiplier6 |) u9 P7 P+ Q4 M, ?; u1 K( p
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Power-down modes
7 G7 C/ n/ E0 M3 w9 P$ k4 u | Sleep mode
( j0 D- s- S' ]- |) P |
Module standby mode5 I$ ^7 i( o; Z) s& w3 @( t& W" ~
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DDR-SDRAM power supply backup mode, [- O4 f; I2 S, j0 L4 ]% W
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Package
# Q' c. |/ l( |9 ^; Z | 449-pin BGA (21 mm × 21 mm)& z2 f4 H+ C4 c: P
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