Overview on ESD protection design for mixed-voltage I/O interfaces

semico_ljj

Overview on ESD protection design for mixed-voltage I/O interfaces
* B) k3 n: E  v$ Ywith high-voltage-tolerant power-rail ESD clamp circuits
in low-voltage thin-oxide CMOS technology

Introductory Invited Paper
6 Q( Q" `7 J; c/ X! f4 y# V: [Ming-Dou Ker

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cedric761193

The ESD is easy implement but difficult to design.

heyunpro

goodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgood

ulysseslaii

goodgoodgoodgoodgoodgoodgoodgood