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Senior Physical Design Engineer2 Q# b* E0 r- F2 l
公 司:A famous IC company6 h. n1 l4 n6 w; Q8 i- p
工作地点:南京6 d: c# i* a" W4 e3 w+ l$ p$ a
; \% S0 @0 P; e3 ^$ p8 @Key Responsibilities 1 {0 j" s; f J0 f: R- F
Depending on experience, key responsibilities will involve some of the following:
% m; F7 J: @+ f( w2 V/ [( J* n# LIC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
) _0 I6 s2 e8 g2 p, z: u* d5 EAs a key member of physical design team, your will work on one of most advanced and the most complex chip designed. - r7 V0 A' \$ h. L0 [
Leading a team of physical design engineers and resolving the technical related issues. ' l% ^ Y5 D/ y, T! O3 K
Crosstalk analysis, power analysis, and static timing analysis.
% b: i& S" j7 ]9 b8 pWrite scripts in Tcl to improve productivity. 2 X1 f- z$ P' r8 ?& _5 m5 `/ i
7 {: _& ]5 {* J9 i2 ~Experience: 5+ years in physical implementation engineering
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5 W+ X5 K, |4 |" ^- xEssential skills ( X- r1 h4 E: n' A3 Q
MS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills & R, Y5 `* m" T9 a4 z" i D
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation.
+ X5 j+ i/ j+ z9 V6 A9 ]# XGood programming skill. Capable of writing Tcl or Perl. : k9 O; u L3 k3 I5 S
Familiar with synthesis, static timing analysis. 4 Z- G! {+ A w! \2 D+ {
Self-motivated team worker, good verbal and written communication skills in English. 0 k' m$ G& `" `7 @/ H" s6 ^- q
Technical and team leadership proffered. Previous management experience highly desired. 7 i: ^0 n( c! _2 @
Experience with synthesis, DFT, and verification is preferred. |
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