[關於] [jianping ]如何用verilog將變數前後補上幾個位元

tommywgt

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因為無法回覆, 所以開新文回答....
! ~2 a9 ?2 I  [) z( yABT={2'b00, DATA, 4'b0000};

6 q' l3 v  w- |& R8 n6 D6 J0 J. ZVerilog 常用的operator
4 H3 F$ A3 ~0 l4 u– Binary bit-wise operators: ~, &, |, ^, ~^, ^~
– Unary reduction operators: &, ~&, |, ~|, ^, ~^, ^~
– Logical operators: !, &&, ||
+ Q! K* a5 p+ i; w" F% @6 s# b; V- l– 2’s complement operators: +, -, *, /, %
– Relational operators: >, <, >=, <=, ==, !=, ===, !==
  [& D8 k$ Z# w– Logical shift operators: >>, <<
; |' T! O% c9 Y3 T$ U9 }7 X– Conditional operators: ? :
; {1 T) {$ \! D' x- Y  V$ x0 `– Duplication operators: {n{ <exp> <,<exp>> *}}
– Concatenation operators: {}
給你參考一下