請問由Verilog code到IC layout 需要哪些軟體

leesg

問題, 已完成 Verilog code 設計, 模擬(ModelSim)
8 p8 ~$ ^) m/ C0 U5 i* J/ r' m想要用軟體直接 run 到 IC Layout 產生 die photo,
要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)
2 O5 E* D* ?* r5 v* o1.
$ @2 z& w7 W% E0 Z6 |( L  T8 ddesign compiler + Astro ?
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1 Q8 H7 U+ ?- y$ P2.
synopsys IC compiler ?
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3.
cadnece virtuso ?

lee100

Synopsys R2G flow
2 t5 m- ^0 M" i- [9 [1. rtl simulation by vcs
2. synthesis by design compiler ultra with dc/dct mode
3. dft insertion by dft compiler
4. jtag insertion by bsd compiler
! u. z6 T' X  }5 b) G6 n; f5. ICG insertion by power compiler
% O' ]2 b( ?! t7 N  f7 a2 Y/ ^6. pre/post-layout STA by prime time
& y- \6 m/ ~! F; s# X2 {7. pre/post-layout power analysis by prime time px
% {# X$ q4 I+ _/ D" _8. PnR by IC compiler
9. post-layout SI analysis by prime time si
% W6 E  b5 E) s7 l. X, N) @6 P10. post-layout simulation by vcs

putechen

sometimes ,star-RCXT is necessary.just for layout PEX.

yytseng

after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.
$ j" x+ z% {/ t0 g1 h9 K* j1 t- ^$ {( |clean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.

ejean

1. magma is another solution
( y$ Z2 v( t6 p  h) Z% i2. Astro  from synopsys
/ y' U+ M$ j5 y/ h3 V3. FirstEncounter from Cadence

- K) Q% T8 p$ s* y  C$ }7 b3 oAll with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.

ilovepachaya

私心推薦APR使用IC Compiler  效果很好