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我在之前的公司有lay過double guard rings,內圍是用PTHIN guard rings,外圍是用4 ^" |7 G U i
Nwell+NTHIN(甜甜圈結構).主要就是用來防止noise,那時是圍在Oscillator外圍.
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Dummy的話,不知道你指的是那部份?? 引述一篇paper " SmartExtract:Accurate Capacitance
2 o3 a% m0 B# K" m- i7 s) Z5 _Extraction for SOC", 這裡提到的dummy是指layout完成後,在每層layer空曠處,補上同一layer / ]# r1 p; j) o/ {
dummy, 為的是在CMP process時,有較佳的均勻性:- o' E0 i( X" c3 h h- P# w
Dummy(or fill) metal is introduced in the interconnect process flow to enable uniform: Y$ B8 v1 ]( s7 F
thickness control in the CMP process. Dummy metal needs to be treated as floating metal
6 n4 \& O: {; {1 K M* H: s# Runless it is intentionally connected to a constant potential. Floating dummy metal
5 l+ q6 U" r6 V' \essentially acts as a capacitance divider.7 q5 O+ Y5 d+ _: `" m6 x, d
另外有一種dummy, 之前我在做analog layout時,會在需做match的mos旁,故意lay半顆或整顆$ A+ b( z8 M0 n6 n) I+ P. E
mos,除了你寫的那些原因,我想是因為實體mos的邊緣不見得是像layout般的四方形(what you draw is not what you get),可能是梯形或不規則多邊形,製程上很難做到如此完美,所以為了確保1 `# a( o1 j: s$ q
主要的mos的完整性及對稱性,在mos旁再多加dummy mos(不要讓主要mos成為最邊緣的部
& i2 B& u3 s6 l9 V4 h7 g) R2 @份).以上是我自己的想法,歡迎各位先進指教 |
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