|
Cadence SoC Encounter 8.1 Update Seminar) t2 e9 X8 z" P8 l Q
& x3 r7 ]% p4 k1 F
- u2 ]# u/ C' k
; K8 i: i: X# f# I0 S想了解Encounter最新8.1 版本強大的新功能嗎? 想知道Encounter 8.1如何協助眾多設計成功案例嗎? 我們將展現Encounter如何讓您的晶片設計smaller, cooler & faster,也提供您處理大尺寸晶片設計的解決方案,趕快參加Cadence益華電腦免費的Encounter 8.1 Update 研討會吧。4 c; _. z0 g; t4 ]
" T9 }% {" N' D1 B1 Z, }2 f8 J
時間:
: v4 ~& n9 m: e( B! {3 o$ Y% Y& n$ O6 j& b/ \, F
Nov. 14, 星期五: 09:00am – 13:30pm - h, ^3 ]" a6 ^4 U- P i* e ?
: l1 T( s3 | ]: a% [' c
& R( o& L0 G9 L! a7 s' B; d2 _, q c% S( p2 n) y$ C! ^& V6 ]: _
地點:. S e) y3 b7 m( P R4 u
9 q5 ?( S5 L! k1 [$ C, U
新竹國賓大飯店13F 會議室A&B (新竹市中華路二段188號)( `* w; N" _* m
/ u4 r: n" g! i' e
( f- e# r! S! M/ {+ x0 Q% s4 l7 {+ A u" h+ f5 [0 v9 R5 R; x
名額有限,請即刻報名!(http://www.cadence.com/tw/events ... ion.aspx?eventid=16)
& z9 y, h& k* Q$ _+ a/ X
( t/ ]4 E; g7 G2 ?. x$ S: G , g! a) r+ F, {. u/ I7 y( G9 W2 t3 o
) s) y. ~" J4 V- |
# w, k3 i, v& C. p& ^' P, S E
2 E. A H! Y X( W5 X; v& D$ |
. b | i8 m: g' n8 S- P+ \0 [/ _
3 x) z) Y" _( ^8 L# i" c
# A9 K) G; I1 Z8 t09:00~09:30 / Registration: p. ?" ]6 Z: l1 g
& L" _( o0 {; e) _) t4 ^+ M2 s09:30~09:40 / Automatic floorplan for design exploration to get the best result' I0 {8 W: |) G
3 H- F/ Q# r& R2 G" K' T
09:40~09:50 / Balanced clock tree to reduce process variation effects
$ M) O8 ` \. ]" J0 [) A
; Q4 l J3 l+ a5 s/ I09:50~10:00 / 32nm support for the very advanced technology + _6 Q: r+ P- A5 Z
: P. v1 L8 o1 r) d" u$ `+ E) O10:00~10:10 / Post route optimization and SI closure productivity - K% h# U/ c. J7 G! R" V9 b# @
- N% Y5 ?& q0 ^
10:10~10:20 / 100% MMMC support in the entire implementation flow- F% O1 k+ \' p: F; z
! g4 J6 F' I2 |+ [& P- n
10:20~10:30 / Dynamic power optimization and low power CTS for power reduction
. T5 p: w- `7 B' e' a3 g! @1 _+ ]' l! `5 U" Z
- j1 f1 j, T4 D7 {6 H( X
2 Z) F+ P# v3 m/ Y& _" {
10:30~10:50 / Break
% V* H9 Y6 D6 D2 S7 h& K
6 f F3 U2 P% Y, C/ U v0 E
1 M& Y+ x9 K+ \, e/ u: S
4 ^# U) F$ {( { l10:50~11:00 / Encounter Power System for new generation power integrity analysis
1 f" {0 a) w s. J( L0 M9 j. v; Q6 S. K9 q! m" X
11:00~11:10 / 3 very advanced statistic applications for better performance 7 g( e; }& T$ X; }! W# C$ v
# F3 N1 A8 ]% v/ g$ i$ M1 X- E11:10~11:20 / Active Logic Reduction Technology (ART) to handle big chips
3 x) ?) B% _+ g- B
% H' k' k$ M ]/ e* z7 X; m# l
5 m- y1 d4 V/ ?& L" L8 O( w( r
% E( o7 X1 _: d/ i1 m) O, K: h11:20~11:30 / Constant run time and memory usage improvements
6 P2 q/ Y4 F. v+ D1 v# d( E
; }6 i; v5 w' L11:30~11:40 / End-to-end parallel computing support( [( Y7 p9 A7 d7 d
! [& i- F" q- r
11:40~11:50 / Encounter Foundation Flow for ease of use and productivity gain
7 B) P/ t+ B- b% a) P9 T$ c' V: u6 ~% _ d
11:50~12:00 / Ending
7 ]& N7 ?2 A8 P. ~
6 C& h& b: |3 ^" f. _: p+ o! j12:00~13:30 / Lunch |
|