LVS問題 望大大指點

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使用LEdit90的LVS時，顯示This file is Binary.LVS can not perform iteration.無法進行對比，這是怎麼回事呀

m851055

是比對檔案中路徑的問題，若有需要詳細說明把netlist PO上來................

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原理圖
* SPICE netlist written by S-Edit Win32 7.03
: `2 V; g, Z/ m, V* Written on May 27, 2009 at 16:57:24
" a. r2 I: c  F% F2 z  d- c' m* Waveform probing commands
3 d) Z" h- ^' ?7 R' o.probe
.options probefilename="G:\tanner\Nand2_1.dat"
+ probesdbfile="G:\與非門2.sdb"
+ probetopmodule="Nand2"
* Main circuit: Nand2
M1 OUT A N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 Gnd B N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 OUT A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
! k( m3 z. q& ?* v7 l9 J: u. |3 ?: g# PM4 OUT B Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
; F. Q7 D' G4 t4 I* End of main circuit: Nand2

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版圖
* Circuit Extracted by Tanner Research's L-Edit Version 9.00 / Extract Version 9.00 ;
5 n) Y, V$ L+ W3 s. s( y: i* TDB File:  G:\tanner\Nand2.tdb
1 P* U' z4 U2 s( S* Cell:  Nand2        Version 1.07
* Extract Definition File:  G:\lights.ext
, S% g+ E* h" k# O" G& q* Extract Date and Time:  05/25/2009 - 15:05
8 W+ W) q, O; ~: W% v+ b* Warning:  Layers with Unassigned AREA Capacitance.
6 v$ C/ V9 K, m! a0 v*   <N Well Resistor ID>
4 {# d+ I1 A* {* G" _*   <Poly Resistor ID>
2 R7 u  X. e% C2 M) g*   <Poly2 Resistor ID>
*   <N Diff Resistor ID>
1 V6 p* s0 q* E, V9 Q*   <P Diff Resistor ID>
  `0 T3 b; E; U; V*   <P Base Resistor ID>
4 {& Q* L3 z3 v" a) Y* Warning:  Layers with Unassigned FRINGE Capacitance.
6 \( D: ^: T$ f$ z*   <N Well Resistor ID>
/ i5 {! H5 G0 I1 f0 z4 T# n*   <Poly Resistor ID>
9 W1 ~6 }9 ~+ l2 q: H* k3 w  N*   <Poly2 Resistor ID>
*   <N Diff Resistor ID>
* R/ `" z( k1 Z! L3 C, y3 b*   <P Diff Resistor ID>
  w5 F$ L/ x7 K: _/ ?5 u, u*   <P Base Resistor ID>
*   <Pad Comment>
& d& G0 [& m& {( k; Z2 g6 \*   <Poly1-Poly2 Capacitor ID>
  ^1 i$ ]! I1 ?0 ^* Warning:  Layers with Zero Resistance.
*   <NMOS Capacitor ID>
7 A3 u% _) U% q. F$ x! z*   <PMOS Capacitor ID>
*   <Pad Comment>
*   <Poly1-Poly2 Capacitor ID>
* E- s5 u& Q# l  `- {
* NODE NAME ALIASES
*       1 = B (12,-14)
. C9 K0 A, f, p$ f# a+ k7 q*       2 = A (-16,-18)
7 e" w% l8 ?0 O: _/ m7 W. o, K*       3 = OUT (-2,-21)
& _3 T' n% |2 x4 i. |( b9 b1 E*       4 = GND (-30,-35)
*       5 = Vdd (-32,14)
+ [  Z8 w8 n% @  _5 qM1 Vdd B OUT Vdd PMOS L=2u W=6u
" D. k6 V' \# N; J* M1 DRAIN GATE SOURCE BULK (3 -3 5 3)
M2 OUT A Vdd Vdd PMOS L=2u W=6u
3 t1 _5 l8 e( O/ o7 j3 C* M2 DRAIN GATE SOURCE BULK (-5 -3 -3 3)
M3 OUT B 6 GND NMOS L=2u W=6u
* M3 DRAIN GATE SOURCE BULK (3 -31 5 -25)
( c! o4 B( G/ {1 W! _$ |M4 6 A GND GND NMOS L=2u W=6u
# ]& J. o/ ?1 n+ q* M4 DRAIN GATE SOURCE BULK (-5 -31 -3 -25)
% j7 `1 r. ?4 E4 a& J+ V% v9 u: l* Total Nodes: 6
7 |9 f; {; `1 E  v& q* Total Elements: 4
- c# b! k8 f. m6 a( f* Total Number of Shorted Elements not written to the SPICE file: 0
* Extract Elapsed Time: 0 seconds
8 r' g3 w, M" Y8 z.END

m851055

與非門2 files name改為英文名稱.......................

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我宅了一周 沒想到栽在路徑上  萬分感謝 ！！！！！！！！！！