When PCB layout area is not enough, we often use 4mil GND trace to shielding RF clock trace with 4mil spacing. 5 Y L1 ~; q+ |0 k8 mIs this way enough to avoid RF clock signal to couple other signal trace near the 4mil trace? & R' R1 d' V( `- @Thanks
u r proposed to refer to 3W rule. 1 r4 ^) b6 U# }! m% t: g. C
when clock trace is 5 mils, u will need 10 mils spacing.. W" x) C* ]- q( Q
of course GND trace will help, but PTH through holes with proper interval will do it better. - F- i( w7 p) ?( ]) A: z) O' A- x) k1 }5 D1 Z
google it for detailed information, please!