When PCB layout area is not enough, we often use 4mil GND trace to shielding RF clock trace with 4mil spacing. $ x& f# o6 ]3 ]3 t2 c9 k7 GIs this way enough to avoid RF clock signal to couple other signal trace near the 4mil trace? ' y2 c0 E" k, U; x; IThanks
u r proposed to refer to 3W rule. / L) [4 X# ~ M1 b- Z
when clock trace is 5 mils, u will need 10 mils spacing.& ^! o$ u; q' ` G) i$ p7 e
of course GND trace will help, but PTH through holes with proper interval will do it better. ! z+ [! C& z# a2 R& L. w) p 7 |# B. P, `. ^& y4 ggoogle it for detailed information, please!