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實驗平台~7 ^. b* L: I. m+ `5 e6 D, x( @
「Terasic」Altera DE0 多媒體開發平台,Cyclone III 3C16 FPGA. O( f/ q$ S6 x. Z' Y' v/ E3 V9 _
在建構的過程中(僅放入cpu跟memory ip)
" J1 k, X$ e( { o, tno reset vector has been specified for this CPU0 S! C* ~0 O/ ]; j" [
no exception vector has been specified for this CPU
6 Z: ~1 {1 o* p) ~- q, U# q4 c這兩個訊息,沒辦法完全消除,這兩個一定要消除嗎
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7 R3 ~# d% ?0 {! a8 S" K( R4 B1 Con chip memory" \, d" D" R5 N4 [# Z
sdram" P+ l8 r% w& m N0 d# H: T/ N0 g
用上面兩個去試過所有可能的組合(mem/mem,sd/sd,sd/mem,mem/sd)5 d3 m- W! ]9 D& ]( l9 S! q* g
no reset vector has been specified for this CPU$ S! R% N( Q) c6 }
no exception vector has been specified for this CPU
7 U h% o5 B, _* G總是會有一個沒辦法去除(先選的訊息會被消除)
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有人有在玩10.1版嗎?請多多幫忙~~
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目前打算~改用10.0sp1跟9.1sp2試試看( U7 v8 P/ N% C. ~( Q; D) z2 S+ F7 u% Z6 |
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