請教如何以兩個clock寫入同一個暫存器?

shlee

假如有兩個Clock, CLKA, CLKB, 當CLKA Raising時, 暫存器A要寫入0, CLKB Raising時, 暫存器A要寫入1, 請問如何以Verilog/VHDL implement??重點是要能Synthesis成一般電路, 謝謝回答..

7 e- Y0 I: ~7 b! ~! @( D5 m' V. t[ 本帖最後由 shlee 於 2006-10-31 01:32 PM 編輯 ]

ssejack1

CLKA rise/ CLKB rise, 如於 asynchronous system 中 使用 gate delay 取的 rise edge 的 pulse,
: @; C1 h" X: u4 i- W& N) F1 q0 b PLUSA = CLKA & (!CLKA_DELAY),PLUSB = CLKB & (!CLKB_DELAY);接下來以 RS 正反器就可以啦!
, ?0 K  N, F. D6 e) M4 r% a
if ( PLUSA = '1') then
4 P  J2 I" x' C1 N8 L" ?   OUTPUT <= '0';
elsif( PLUSB ='1') then
. M9 {1 ]  T; n5 R, h8 y$ {  OUTPUT <='1';
. P) D& [1 V& ~2 K! w/ t; T& q* wend if;

fpgacpld

Actually, you must check the library, for example, when using Xilinx FPGA.
They provide Dual Edge FlipFlop, You can just instantiate it.
' G& r( u0 K' I+ S/ a
. T6 I/ l/ z) E9 S( vIF you're using ASIC or Other FPGA product, usually they also provide similar component!

the attached example fdd.jeg is the Xilinx Dual Edge FF component!

tommywgt

如標題所示, 這是一般的做法, 使用FPGA時就如同fpgacpld所講的呼叫library, 用ASIC的話也是有相對應的library可以用