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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題
! d2 G  t( u" g; }
3 m  W! D- N" X$ l( @請教業界各位先進
- W/ }: m6 M, f  @- j# H目前的chip開發,需要多少投資?
0 u' _7 e# ~% Q7 n  g首先是假設 Febless design house.+ O/ G) c, S* W: Q
自家由algorithm 到 RTL simulation 完成
7 F- ]  F/ o6 B5 Y8 S, G( \# V) g後端包給 backend service 公司 (layout, mask, Fab, assembly..)9 F  {9 V- b) [! }
以 ARM9 or ARM11, AMBA2.0 為platform
, |6 ^; a# P5 A. a6 C" k那麼3 q  q* \& @5 Q
  (1)90奈米, NRE大概多少?
: v# d3 A& ?; ~0 c% Z  (2)65奈米, NRE大概多少?1 h6 Z7 C5 V1 T, s' S
  (3)或是您知道其他製程, NRE大約多少...
, D8 U4 [$ ]& u7 X  n4 M
/ k. [! M5 f# y5 P* W+ O  E: w1 X' f謝謝
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?
9 l( ~+ q* M) z7 WHow many mask layers it will be?
* p4 i' {, P  k6 r) eBesides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?
' |$ ~6 X  D+ z5 yHow many chips you need? A full set mask or MPW?5 a, U: q/ {% j6 |5 N
What package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,
9 a- e+ ^) n" ~0 b- D
& O( L3 }- j' ^I just estimate the investiment of a ASIC team.* i& R# K# G# }' p! E7 S1 v
not servey for a project.$ O6 d& R7 E5 F% a0 M3 x
So, I just want to know the range of NRE.3 Q6 x5 f% x" q. T! ^3 A3 C
8 J8 U  h8 ]; F4 o
For example, It will be
* E/ B% ~; T  @(1) 5,000,000 NT$ ?
. T3 M& P4 D# |* ]# P5 [. @(2) 8,000,000 NT$ ?
7 `* k& b' C" Y(3)10,000,000 NT$ ?  z2 W2 c. V) c6 R: T
(4)12,000,000 NT$ ?1 F# o1 }# ?. d  w7 b: q5 s
(5)15,000,000 NT$ ?4 u3 r! Z# Y# B4 S6 z
+ i# P7 }4 z; n/ b7 r! {
Sure, I understand following things:. J% h" F; N. _* x' M" g
- full set mask cost more
7 w4 L) O! ^9 y5 J- a) L- k; G - PLL/LVDS... analog IP are extra cost1 U, o" @9 J/ C/ U9 P
- pin-count and area also influence cost
1 L1 z" C" j" e - different package also cost different* W4 D1 x: _5 u; F7 K6 S, S
  B# Z1 R/ }2 S/ H* m- q6 f* i+ f- K  Y
Therefore, if really need information for estimate,7 R( T1 @1 {* A5 @- M
just for example.- z7 V: w9 z" \, T% K
Let's assume a SoC for FullHD TV application" o: v2 S" g* a2 I1 d
it will include
# n, J4 ?- F- ~  - ARM AMBA
* d, u! X. }: x0 ~# R: E. d$ l  - DDR2 I/F3 u  U( p1 |8 V1 W2 L
  - GPIO, IIC,...
9 R/ m' g, ?& X; o& Y  - LVDS out (dual link)
. N* i, f$ i5 S' n; o) F6 v  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,
; r% O% X' I; n# M4 _4 d3 v9 z  - 12bit ADC, 10bot ADC x2
) W; F" x; r: H6 U4 l$ ~& o2 t) U  - PLL/DLL: K' k8 s" c1 p$ R
  - 256 pins 以上6 u/ L: b: ?" D" ]1 ~' X6 F* ?

4 ^  F) `" j! T, z4 \Than,... any idea about NRE fee?% w% w! c! W  }3 G
again, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,
! H/ y) L, A9 w5 e0 Ybasically 65nm-->USD$1M above and 90nm-->700K above
5 J+ u2 _( U& D$ r( C+ dand base on different foundry has difference price!
$ C/ _5 a0 K) y% W1 fthis price did not include any specific IP like TV encoder, decoder, vedio codec....
, N% I( D# _, R2 l- g. B- land did not include the ARM licensee...; m: C4 L4 L7 V/ C2 u  `
actually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)
! h: f; ?5 ^" x5 t( u$ }+ Z- fand package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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