hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs
0 I7 a& K5 {. n1 o
要怎麼定義用
; e# C, \# y$ C3 o: k0 qplot LX??

' F! }" e1 R! |, S請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .
0 I# \: K# `7 |1 ]
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.
  C2 V4 X* c) O2 k8 b
+ L) g3 N/ h' V2 m" j
( t) q8 b: w6 i* J% q' t, bFor your reference.

0918429587

CAB_BS    LX28
7 D- B8 z/ H; n1 e+ ^$ s! FCAB_BD   LX29
+ m) s9 E( a7 V+ T- x3 N- s  }
其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
7 P( J7 S0 ~! U5 i) a5 K這是 CGDBO  CGSBO CBGBO
* S( J# \" w  j& g+ o. K
不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
2 O$ X. H6 d) c' jAn example for your reference...

9 v1 n% {5 A4 u: U" [* H. F' G% A----------------------------------------------------------------
***** Gate Capacitance Plots *****
% L4 _& ]9 R2 n  z3 T8 U  n0 t.lib 'your_component_model' lib_corner
.temp operational_temp
.option dccap=1 post
m1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
vg n_gate gnd 5
vb n_bulk gnd 0
.dc vd 0 5.0 0.1
.print   CGG=lx18(m1)
2 m  X* q" T+ G' Q+        CGD=par('-lx19(m1)')
+        CGS=par('-lx20(m1)')
+        CDG=par('-lx32(m1)')
+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
.ends

----------------------------------------------------------------
Six capacitance are reported in the operating point printout
1 e9 ^3 n7 a- N; ^    cd_total = dQD/dVD
    cg_total = dQG/dVG
2 L* C' [! A7 J: c0 j) q" J    cs_total = dQS/dVS
    cb_total = dQB/dVB
* ]' i7 q* d( F9 I5 I    cgs = -dQG/dVS
    cgd = -dQG/dVD
0 l: O4 w* i/ O; L7 [. w, yThere capcitances include gate-drain, gate-source, and gate-bulk
7 x$ ]# G7 L% R! Z% H9 L. N3 K! Hoverlap capacitance, and drain-bulk and source-bulk diode capacitance.
" D  R. D- }# `7 R) G/ H
CGG = dQg/dVG
8 D! W% P8 _, HCGD = -dQg/dVD
CDG = -dQD/dVG
* n% @; H3 B' c2 |2 o
3 }/ {- e( c- {' AThe MOS element template printouts for gate capacitance are LX18~LX23
" F4 ?9 r. u/ t; B5 V4 Z" land LX32~LX34.

LX18(m) = dQG/dVGB = CGGBO
' y+ i# g' A1 o% @- PLX19(m) = dQG/dVDB = CGDBO
LX20(m) = dQG/dVSB = CGSBO

LX21(m) = dQB/dVGB = CGGBO
LX22(m) = dQB/dVDB = CGGBO
& W* N' m# t: z" ]LX23(m) = dQB/dVSB = CGGBO
8 d' G8 q+ x) Y( i% b
LX32(m) = dQD/dVG = CDGBO
8 m7 W9 d0 E! f7 ^# X  i# J, V" D; @. ZLX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO
4 p3 y' s+ g- z) s7 h! ?
2 X5 d% U7 b- r' ZThe equation shown above is for an NMOS with source-bulk grounded
1 b4 |) L. w5 m  d  fconfiguration. Refer to the user's manual for more detail ^^