hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs
2 U( i6 a- _% [) O0 J7 S1 b" x
要怎麼定義用
$ ^6 p: n7 m6 ]plot LX??
8 H4 |, R1 X1 q- A' i  j9 t
請各位幫忙一下

小朱仔

直接下.op及.probe
. m! j6 [, K7 M/ z0 l& G& o) _* f+ N找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .
" A) s* M) F: r" p: z" `
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.

6 Q4 Z* T! ]: G( i- r; y. n% e
+ |7 b: r" L' z: e! I: C4 xFor your reference.

0918429587

CAB_BS    LX28
CAB_BD   LX29
; Y+ S* d8 }; U+ d4 k% ~
. k1 o; T1 \/ A其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
這是 CGDBO  CGSBO CBGBO

% y% G1 N, M  j$ Z1 |) }不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
1 V( @+ x" z6 C1 Y  _: d  |! HAn example for your reference...
3 ^4 _/ S; L# m
----------------------------------------------------------------
***** Gate Capacitance Plots *****
1 M# L- s( T3 F.lib 'your_component_model' lib_corner
/ U1 ~! L2 [" j  ?  u7 k# I) z.temp operational_temp
+ g2 K9 F+ _) S6 {3 F( Q6 p.option dccap=1 post
m1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
' y* Z& |7 a0 f/ L) R: vvg n_gate gnd 5
vb n_bulk gnd 0
) c& r; Z8 B+ |9 _6 }& S8 E.dc vd 0 5.0 0.1
.print   CGG=lx18(m1)
+        CGD=par('-lx19(m1)')
+        CGS=par('-lx20(m1)')
; j7 n; J1 M( T- O. ^# S" ~: l+        CDG=par('-lx32(m1)')
9 z6 t5 L4 A( I+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
; D5 s6 ^5 `' p+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
.ends
5 N5 }0 ?* O3 |% J! r) K; y4 C
  G; X# G3 Q; a$ o4 r. t6 h1 @----------------------------------------------------------------
Six capacitance are reported in the operating point printout
    cd_total = dQD/dVD
    cg_total = dQG/dVG
! \4 |0 ~7 e7 H2 S" y4 ^; K5 n    cs_total = dQS/dVS
$ U# @  t; O: V( S, [    cb_total = dQB/dVB
    cgs = -dQG/dVS
    cgd = -dQG/dVD
& g; q; X) Z3 q. Q4 `& w2 O2 EThere capcitances include gate-drain, gate-source, and gate-bulk
- Y2 R, q: d  ~5 W+ C# b& b; roverlap capacitance, and drain-bulk and source-bulk diode capacitance.
$ j) K! J; {) q! k% j& N
# w( J' Q, g- w) D/ R/ PCGG = dQg/dVG
' X3 Y& l( s2 o0 h) {3 X) U" D" kCGD = -dQg/dVD
1 z" w* |/ |8 _% J5 p1 }CDG = -dQD/dVG
% Y/ {. z/ r7 G" q0 i5 X! B* R6 k& ]/ X% |
5 ?3 P, G2 M/ SThe MOS element template printouts for gate capacitance are LX18~LX23
; o2 y) y! f  e8 Y& U/ pand LX32~LX34.

! g" L9 y. ?; v! GLX18(m) = dQG/dVGB = CGGBO
, T; Z9 h6 K; X$ V2 x; z, ]" JLX19(m) = dQG/dVDB = CGDBO
LX20(m) = dQG/dVSB = CGSBO

. S& z5 T* k% x5 ]0 y3 Y- uLX21(m) = dQB/dVGB = CGGBO
LX22(m) = dQB/dVDB = CGGBO
* @, c' n" _6 k# Q, F  |LX23(m) = dQB/dVSB = CGGBO

LX32(m) = dQD/dVG = CDGBO
) }3 F/ |+ X. j: f' H* Y5 C4 N0 oLX33(m) = dQD/dVD = CDDBO
5 d# n1 o3 `& e+ W( P0 o% vLX34(m) = dQD/dVS = CDSBO
/ R: [9 j1 N2 X
The equation shown above is for an NMOS with source-bulk grounded
- G$ D0 ?& k7 x- Q' l3 N/ oconfiguration. Refer to the user's manual for more detail ^^