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AMD Geode LX 800@0.9W處理器
General Features
4 V- }! Y% c: a" j$ H■ Functional blocks include:
4 r, c# b& o1 q' I# t5 Q9 x9 d— CPU Core) z2 k. B, N6 i% D
— GeodeLink™ Control Processor8 T0 }- R8 L$ G* n, D6 _$ {
— GeodeLink Interface Units* O" ?( R# G! J% J- X6 Z' ~2 Z6 S
— GeodeLink Memory Controller
$ i% E5 H0 Y$ b— Graphics Processor
% [ ~5 b9 _: O: V; G- [— Display Controller8 h. R0 F5 t3 `
— Video Processor# e5 p) F9 l! V3 `4 c
– TFT Controller/Video Output Port6 T: P! v( {( b9 U& s" ^
— Video Input Port& n9 G; v- V. y$ n; D1 X% e
— GeodeLink PCI Bridge
$ g3 v) O1 S& o( H, E8 o— Security Block
1 Q2 e! t: x$ }■ 0.13 micron process7 s, T3 q# j! p# [! E
■ Packaging:6 W! b+ _9 ?2 K: W
— 481-Terminal BGU (Ball Grid Array Cavity Up) with8 P* C4 [6 c3 \
internal heatspreader! \. C/ q2 K( V. i& X( }8 d8 l8 \
■ Single packaging option supports all features
6 k5 Q* N3 @" g: U# Y$ e _ SCPU Processor Features( }! f6 l$ [* w! S" n, J& Y+ Q: G
■ x86/x87-compatible CPU core# G9 E* a1 S8 k- |) i
■ Performance:' L% U3 x% y0 a; n
— Processor frequency: up to 500 MHz
) c- P+ [# ^3 {" C— Dhrystone 2.1 MIPs: 150 to 4503 k& I) A4 Q8 ~1 _* A
— Fully pipelined FPU: ^, w9 l9 s* b. |0 w
■ Split I/D cache/TLB (Translation Look-aside Buffer):: J( X' ^+ f9 L
— 64 KB I-cache/64 KB D-cache
2 C( d4 k0 \' E9 r: C— 128 KB L2 cache configurable as I-cache, D-cache,/ Y2 U$ i1 r$ R- L: P8 y4 o: y
or both
# T# g* n6 C' M2 m% e! J$ s■ Efficient prefetch and branch prediction% j& e8 \, G4 }+ Z0 b" N
■ Integrated FPU that supports the MMX® and
1 r6 n/ m. P0 B& q6 WAMD 3DNow!™ instruction sets& \. N9 O' d: d, G' \
■ Fully pipelined single precision FPU hardware with
# S, u. e3 f( d, u- ^! j4 omicrocode support for higher precisions
( s4 _3 N% z, d" l$ d! FGeodeLink™ Control Processor
# Q2 Z! l% J9 _0 [* J8 R- D■ JTAG interface:
( g0 Q2 d, {) W! r& R— ATPG, Full Scan, BIST on all arrays% |, n+ i! R' @ U" l$ M
— 1149.1 Boundary Scan compliant
5 S$ s+ A# P' F' h( ?■ ICE (in-circuit emulator) interface
1 F4 T2 y; F1 i: X■ Reset and clock control1 }7 P: g M" C {
■ Designed for improved software debug methods and
. B! w* ]7 E5 b6 U5 H! A7 [performance analysis# B- k6 R! h$ \9 j4 S0 u
■ Power Management:
% R% ?$ C% ~% g' D— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
* q; v6 j" F, N2 \; Z" }500 MHz max power% @) S; ?! h; Z! W( P. v
— GeodeLink active hardware power management/ c; W3 O' m5 u% b, b3 @/ c
— Hardware support for standard ACPI software power$ ]& A4 y4 h, c, I* r
management/ `7 A% q% z3 N: l1 X
— I/O companion SUSP/SUSPA power controls
" N4 ?$ }0 A- T% E— Lower power I/O
3 k! Y6 ^' v, L: @2 k1 b; q6 v9 x3 a— Wakeup on SMI/INTR
" ]; ~7 t! e" K& @■ Designed to work in conjunction with the
! b: ^, \0 ~0 W1 L t QAMD Geode™ CS5536 companion device
- f7 o8 s4 O# KGeodeLink™ Architecture# P) Y/ W. u" u! } f( s
■ High bandwidth packetized uni-directional bus for7 j) H! z" T" l7 U( {5 S5 Y
internal peripherals
" J1 ` O4 v# T* C- B■ Standardized protocol to allow variants of products to be& J1 Y8 i$ g' T
developed by adding or removing modules0 L5 V. `8 V9 s
■ GeodeLink Control Processor (GLCP) for diagnostics
5 t: u0 }( F- i; u vand scan control
( E/ d* x' M6 y8 w* d# K. S% K: W■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
: s6 T8 q/ j: L4 n# Z0 YGeodeLink™ Memory Controller2 S z5 J' H0 w6 U# Q7 D9 W
■ Integrated memory controller for low latency to CPU and
: v2 l8 [1 @( c% k; k* H' @. non-chip peripherals( c6 K4 ~& N* U2 a/ l9 S) I1 f& [
■ 64-bit wide DDR SDRAM bus operating frequency:
+ |# R# G) _$ W! ~( g) y- s; n' U) S— 200 MHz, 400 MT/S
; J- b, k5 ]# F# S3 x' C7 B■ Supports unbuffered DDR DIMMS using up to 1 GB7 r) R/ m f3 {2 z
DRAM technology6 ]& `' n3 V1 G+ O& x
■ Supports up to 2 DIMMS (16 devices max) v- s! n8 x3 a! a0 Q) }+ B
2D Graphics Processor8 D8 n* l4 `7 D" \, ^% Q% S& i
■ High performance 2D graphics controller2 C X2 F" B# s, y0 \7 C( {8 Z
■ Alpha BLT
6 i7 }1 h2 S4 U {9 c1 G■ Microsoft® Windows® GDI GUI acceleration:
% b/ r7 _/ A3 Q6 r5 r— Hardware support for all Microsoft RDP codes. w# n- Y5 C* C! H7 b/ |4 c
■ Command buffer interface for asynchronous BLTs Y7 [" Z( c1 Q- x% X4 a8 Z2 |
■ Second pattern channel support$ {. s. l) y/ J( n/ n, N
■ Hardware screen rotation |
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