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Standard Cell 的 Data Prepare 的過程我會去做 axgDefineWireTracks8 w: I8 l: r0 }$ S- `. H
然後再做 axgCheckWireTrack 來 check wire track, 但是做完 axgCheckWireTrack
& c0 A8 _$ ]: `. a& C2 D之後卻有如下之 Meaasge:
: |* F* f& p$ U4 Y' L
- Z' T, P1 H, o' f, n2 S6 `******** Pin Access Analysis *******
; i- T6 `3 k% F1 h% C** # Cell Masters = 1000! l2 Y ~7 y2 H' C7 v4 `
** # Ports (logical) = 25001 _( @9 f2 X- {9 w o- E
** # Pins (physical) = 2500
: T& r9 W1 z( _2 ?- B" Q: F+ L** # Pins with no good access point on Grid (V&H) = 5 ( 0%)! d f, d4 @6 a- [$ \1 `+ M+ }
** # Pins with no good access point on Ver-Grid = 5 ( 0%)# E7 g* Y, i5 [5 s$ W5 Q
3 _7 C! x4 y [( e4 `8 j
請問下面這兩句是代表什麼意思呢?# Y6 U, s: P0 o
** # Pins with no good access point on Grid (V&H) = 5 ( 0%)8 J0 o q3 n3 L9 m5 J# a
** # Pins with no good access point on Ver-Grid = 5 ( 0%)* h/ e @9 k, {4 K6 P- U8 J
. G1 ^8 H; Y1 M若是代表有錯誤的話是否要 Fix 呢? |
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