Optimization on ESD Clamp Circuits in a 0.13-μm Technology

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Optimization on NMOS-Based Power-Rail ESD Clamp
Circuits with Gate-Driven Mechanism in a 0.13-μm
CMOS Technology

* O. ?! Z4 I2 v% ?, EAbstract—NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the
8 z& H# z7 _; C1 Q% v0 G+ Adesired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.

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IV. CONCLUSION
9 j- ]! H& s+ E, E6 x* I3 ]The designs with 3-stage-inverter and 1-stage-inverter
controlling circuits have been studied to verify the optimal
design schemes in NMOS-based power-rail ESD clamp
circuits. In addition, two ESD clamp NMOS transistors,
0 r8 L( ]  P% `9 b1 y- f# Jhaving snapback and no snapback operations, also were codesigned
with different controlling circuits to realize the
impact on their required performance. According to the
experiments and analyses, the 3-stage inverters can slightly
increase the ESD robustness, but they also can dramatically
5 H- g  X9 T3 U5 m) G1 ]' \sacrifice the mis-trigger and latch-on immunity. The 1-stage
inverter should be an appropriate and reliable candidate for the
power-rail ESD clamp circuits.