hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs

要怎麼定義用
plot LX??

) _- t# X# |) O& k  D6 m7 [* H+ J請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .
; `' h* t& m" a  A. l
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.
+ d+ l! {& N, R  W+ v! u
9 Q1 b6 u7 ?' |/ |/ O9 Q: t
For your reference.

0918429587

CAB_BS    LX28
3 e* N  b7 j, SCAB_BD   LX29

  ?; L4 Z7 R/ a" ?( D; r其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
! t7 i2 y9 D) I% ?+ J, J3 c1 t這是 CGDBO  CGSBO CBGBO

; c( V0 d. B7 [: R9 M0 ^7 |不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
An example for your reference...
) Q5 l0 J' F! k+ `9 {
* A; b& g4 }' |! Z/ Q- m9 k  i) o----------------------------------------------------------------
***** Gate Capacitance Plots *****
.lib 'your_component_model' lib_corner
.temp operational_temp
.option dccap=1 post
. h' [# Z3 u& X, \" Mm1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
vg n_gate gnd 5
1 {' Y, F2 R1 hvb n_bulk gnd 0
5 [. e7 t/ w& V3 c.dc vd 0 5.0 0.1
3 z( T8 t6 R2 I0 _.print   CGG=lx18(m1)
! q* u$ m, X. l0 t+        CGD=par('-lx19(m1)')
! y; {! U/ W! `. P: @" u+        CGS=par('-lx20(m1)')
+        CDG=par('-lx32(m1)')
- Q, p  B7 j* b' V6 a$ z7 e+ p+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
7 S, U8 j; O/ B- i# f.ends
- x- I5 T% n' `! H1 u6 I' l
----------------------------------------------------------------
Six capacitance are reported in the operating point printout
1 N  s1 [! o) Q0 z# R    cd_total = dQD/dVD
    cg_total = dQG/dVG
    cs_total = dQS/dVS
* v2 }6 h( F1 `6 D0 p' l" J    cb_total = dQB/dVB
    cgs = -dQG/dVS
    cgd = -dQG/dVD
There capcitances include gate-drain, gate-source, and gate-bulk
overlap capacitance, and drain-bulk and source-bulk diode capacitance.
; _: O" g$ ^% ]& w  d5 x
) Y9 j8 q$ ]; ?0 U, XCGG = dQg/dVG
CGD = -dQg/dVD
CDG = -dQD/dVG
5 G! z# _" }' Q* A
The MOS element template printouts for gate capacitance are LX18~LX23
' |+ T* X/ w( U3 X$ v7 `3 r4 z( uand LX32~LX34.
4 F# @. B& P! _: o! K% s( V
LX18(m) = dQG/dVGB = CGGBO
4 E  i$ a3 d. s* mLX19(m) = dQG/dVDB = CGDBO
: e) F: `) j6 \3 ]( e0 K! S( KLX20(m) = dQG/dVSB = CGSBO

LX21(m) = dQB/dVGB = CGGBO
% S3 q( J9 j8 r; h6 }LX22(m) = dQB/dVDB = CGGBO
LX23(m) = dQB/dVSB = CGGBO

LX32(m) = dQD/dVG = CDGBO
- G/ K' ]. Y) l+ u% }8 X3 A) j2 yLX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO

1 l! D0 J1 ~* D) P: Q8 VThe equation shown above is for an NMOS with source-bulk grounded
3 `0 C1 L  b* O7 sconfiguration. Refer to the user's manual for more detail ^^