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LOAD SDC FILE時. n" Z( X8 z5 @0 O2 H7 L' e% }
Astro 訊息
. P; t' |5 b, {, d& X---------------------------------------------------------------------------& H1 K+ K' b6 N/ @: w
Info: starting Tcl processing
) K" c6 E( T" Y" W lInfo: building design object name tables @" M) q: @0 ]( _9 W" F/ r
Warning: No pins matched 'TOP/test/mul/A[26]' (SEL-004)# v7 E' P" F& r/ K# t9 } r( l
Warning: No pins matched 'TOP/test/mul/A[25]' (SEL-004)
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3 l9 j. o( y& s# [, jSDC FILE& R9 x+ o1 w! h" i
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set_multicycle_path 9 -through [list [get_pins \$ D/ h4 }; L( e J
{TOP/test/mul/A[26]}] [get_pins \8 V: h Y5 V, `& C* h$ Y
{TOP/test/mul/A[25]}] [get_pins \
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: G8 @7 B' {( c2 ~Verilog File
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uniquify_mul_0 mul ( .A(icwAeYfSum[26:0]), .B(" h& t3 R$ Z, O1 H% k8 {
icwAeYfNum[18:0]), .C(ae_avg) ); |
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