Item
5 i" J* T6 ]6 h* a | SH77722 (SH-NaviJ2) Specifications
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Type name
5 {- E' ^8 z; U6 I" O+ V+ Z% m | R8A77722DA01BGV3 {: ^" a- ]4 Y! S% C
| R8A77722DA02BGV
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Power supply voltage
4 a2 d- r+ v5 w8 F | 1.15 to 1.3 V (internal),
9 j* M" s9 f) k F |' Y3.3 V and 1.8 V (external)
4 _8 J# U6 n V | 1.2 to 1.35 V (internal),
' V1 l) P9 P4 m7 W) M K3.3 V and 1.8 V (external)
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Maximum operating frequency
+ r ]" D+ X x) p/ c | 336 MHz' F# r' M' u7 C0 G+ b0 l
| 400 MHz
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Processing performance
' E$ z7 B% _9 S% T" u0 X" Y9 w | 600MIPS, 2.3GFLOPS
& v9 \4 e8 A" N- ?* n | 720MIPS, 2.8GFLOPS) f+ ?- f; T1 w9 Z1 @; I/ A* y& c
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CPU core
& _& w2 q+ P# { | SH-4A core4 L# w- t9 c, H- N
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On-chip RAM
& ]. A( _/ z' W4 k | ILRAM: 16 Kbytes: `0 w8 z5 R; K
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Cache memory2 R! u+ ?. R& E, H9 K
| 4-way set associative type with separate 32 Kbytes for instructions and 32 Kbytes for data
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External memory: A; W1 N- f. q X
| DDR2-SDRAM (data transfer rate: 336 MHz) directly connectable to dedicated DDR2 bus
4 P2 ^' P3 `4 u, P5 Z | DDR2-SDRAM (data transfer rate: 266 MHz) directly connectable to dedicated DDR2 bus, j" F( {: d. k- `) e
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SRAM or ROM directly connected to extension bus* `, A% V3 H3 J- T/ z4 D1 N! q
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Extension bus, I2 H7 s ]/ ^/ ?9 u' v4 u7 \1 H
| Address space: 64 Mbytes × 3* d. W7 ?& Z& Z, m) R8 T9 c I3 w
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Main on-chip peripheral functions
+ E$ j! {4 b$ t* R3 S | Renesas Graphics processor(2D/3D)
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Display control: outputs for two screens (digital RGB and LVDS)
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Video input interface
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SD card host interface × 2 channels
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USB 2.0 host/function interface9 T9 W5 ]; x1 ^! J! N) O
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FM multiplex decoder, V. r6 O* T$ L6 j# i
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Controller area network (RCAN) interface × 2 channels
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MOST interface module& f3 N+ v y* w" ^7 r
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Various audio interfaces × 4 channels2 e K; u: ~ D) ^( F
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Dedicated DMAC × 26 channels u4 b6 n% h" ?* j; M
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I2C bus interface × 2 channels6 C2 ~ J- J8 K2 H6 `1 n# u
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Serial communication interface (SCIF) × 8 channels4 g- J0 x$ {7 m4 U" G
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Remote control interface × 1 channel6 Q% c4 a: ?# r) Q! m5 K
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A/D converter (10-bit) × 4 channels7 I/ R5 j7 I- {. A _
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Timer × 9 channels- C! M- x8 H! g+ Q& S5 N# f
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On-chip debugging function
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Interrupt controller (INTC)8 T$ N& X& C8 s% Q2 |
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Clock pulse generator (CPG): built-in PLL frequency multiplier
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Power-down modes
# z% b* x1 ~* w7 @; \; D- I | Sleep mode
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Module standby mode
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DDR-SDRAM power supply backup mode
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Package; \9 M, h" x+ s3 Q4 q. E1 @. W
| 449-pin BGA (21 mm × 21 mm)9 g& @- T: w" y( w% o( k/ F
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