在鎖相迴路中如何決定迴路頻寬K呢？

kmchen3089

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(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一
# \8 [/ q# U# ^3 P否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump
pll ,且亦有unstability issue
7 A, G: v- Y6 \(see Charge-pump phase lock loops paper by Gardner
" S+ p% r: X; F# v# a$ V; L9 Z' jIEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980)
3 B- b) n6 N# n2 G$ o: B(2) loop BW is related to jitter (or phase noise) ,and locking time
" r3 ~* x0 Z( g+ J) ~( u0 b$ Cso you have to consider loop BW  from jitter & locking time  spec
(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq
(4) In my opinion ,gain margin is not considered in pll design