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Startup's software turns uniprocessors into multicores+ b8 { G* r6 {. W
6 ]( v4 z3 u* {; p1 C' A3 qAmir Ben-Artzi . M' ^. G5 K7 e3 W: u
EE Times Europe
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$ w9 M" K& Z* H, X& Y* ^- CNETANYA, Israel — Startup Mplicity Ltd. (Tel Aviv, Israel) has developed a technology that it claims can, working from an original netlist, turn a single-threaded system, be it a processor or any other combinatorial logic, into a multithreaded system, with a performance improvement of up to a factor of four. 1 s& ^. ?% W, V# ^
! x E* T, [( e% uMplicity's software is called CoreUpGrade and is independent of processor architecture, the company said. "The CoreUpGrade seamlessly transforms a given single-processor core into an enriched multi-core with a significantly reduced cost to performance ratio; it is also designed to compress large blocks of any repetitive logic," the company claimed at its website. 8 D% s! z3 ]0 L# \ C7 e% m; X! d" J
; c0 i( H: ?) f, _- VCoreUpGrade can provide support engineers who want to perform an engineering trade-off between die area and clock frequency which equates to a business trade-off between cost and power consumption. % x2 A; c3 b! s8 j3 Z0 x
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5 U9 \5 V: M* f! \7 X( aProviding an example CoreUpgrade's capability Mplicity has taken a single-core ARC625D from ARC International plc (Elstree, England) capable of performing at a 270-MHz clock frequency and transformed it into a dual-core processor capable of performing at 237-MHz clock frequency across the two cores. The result is an silicon die area of 0.484 square millimeters, instead of 0.354 square millimeters but with 27.5 percent improvement in MIPS/area ratio, Mplicity said. 3 s. ^1 ^0 t1 A/ \* C( ~9 ?
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The "dualized" ARC625D is a cycle-by-cycle compatible component which can be integrated with standard EDA tools and fab processes. ( \1 R) f) k9 c; C! m( U
( u' m" y1 r2 {- F. oCoreUpGrage is applicable for any repetitive logic and can be used to optimize a variety of existing RISC, CISC and DSP processor netlists, by enhancing processor performance, while reducing silicon footprint and power consumption.$ ?0 u$ u. y1 c# b
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[ 本帖最後由 masonchung 於 2007-4-26 06:21 PM 編輯 ] |
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