以色列新創公司發明EDA軟體 能把單處理器變多核心

masonchung

Startup's software turns uniprocessors into multicores

Amir Ben-Artzi  
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04/02/2007 12:14 PM  
( R4 }0 D9 J4 M( Z- y  @. k* mNETANYA, Israel — Startup Mplicity Ltd. (Tel Aviv, Israel) has developed a technology that it claims can, working from an original netlist, turn a single-threaded system, be it a processor or any other combinatorial logic, into a multithreaded system, with a performance improvement of up to a factor of four.
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Mplicity's software is called CoreUpGrade and is independent of processor architecture, the company said. "The CoreUpGrade seamlessly transforms a given single-processor core into an enriched multi-core with a significantly reduced cost to performance ratio; it is also designed to compress large blocks of any repetitive logic," the company claimed at its website.
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CoreUpGrade can provide support engineers who want to perform an engineering trade-off between die area and clock frequency which equates to a business trade-off between cost and power consumption.

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Providing an example CoreUpgrade's capability Mplicity has taken a single-core ARC625D from ARC International plc (Elstree, England) capable of performing at a 270-MHz clock frequency and transformed it into a dual-core processor capable of performing at 237-MHz clock frequency across the two cores. The result is an silicon die area of 0.484 square millimeters, instead of 0.354 square millimeters but with 27.5 percent improvement in MIPS/area ratio, Mplicity said.
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$ ^" c. _5 ~: IThe "dualized" ARC625D is a cycle-by-cycle compatible component which can be integrated with standard EDA tools and fab processes.

1 }* ~, t- e4 Q$ i" L2 L$ _CoreUpGrage is applicable for any repetitive logic and can be used to optimize a variety of existing RISC, CISC and DSP processor netlists, by enhancing processor performance, while reducing silicon footprint and power consumption.
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[ 本帖最後由 masonchung 於 2007-4-26 06:21 PM 編輯 ]

masonchung

The startup targets compute-intensive market segments that use large amounts of repetitive logic or face footprint or system power constraints. Typical potential customers are developers of ICs for next-generation portable equipment such as PDAs, cell phones, GPS and mobile computing platforms. Mplicity has been working for Flextronics International Ltd. (Singapore) and Ceva Inc. (San Jose, Calif.) among others.

Ceva launched the X1641m a Quad-MAC DSP core in the scalable CEVA-X family in October 2006. The X1641 is designed to run computational intensive tasks that require substantial data throughput and high memory bandwidth. The CoreUpGrade offering is based on virtual multiprocessing (VMP) algorithms and tools which enable designers to reduce the number of wasted clock and instruction fetch cycles, thereby reducing cache size requirements as well as improving the average gate utilization factor (GUF), according to Gil Vinitzky, chief executive officer.
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! I7 p( U9 d) \Mplicity was established in April 2002 and employs 12 workers. It was founded by Vinitzky and chief technology officer Eran Dagan. Vinitzky and Dagan worked together in senior development jobs at fabless chip company DSP Group Inc. (Santa Clara, Calif.). Dagan and Vinitzky raised their initial capital from Stage One Ventures and Alice Lab. The two venture capital firms initially invested a little less than $1 million in Mplicity, but also undertook to make follow-on investments as part of a financing roadmap. The company has recently standardized on the Formality equivalence checking software from Synopsys Inc. and its retiming verification methodology for CoreUpGrade customers.

phoenixson

it looks like a mulit-threads mode,not a multi-core cpu.

chip123

發佈時間：2008.01.19 10:12     來源：賽迪網    作者：天虹
http://big5.ccidnet.com:89/gate/ ... 0119/1347827_1.html

【賽迪網訊】1月19日消息，據外電報道，據密碼專家Joseph Ashwood稱，在21世紀，微處理器廠商開始採用多內核結構執行並行計算。然而，記憶體晶片結構卻沒有跟上這種變化。他說，他已經創建了一種新的21世紀的記憶體晶片架構，通過並行、同時訪問多個記憶體晶片的方法來滿足多內核晶片的需求。

Ashwood是住在美國加州Gilroy的一位獨立安全密碼專家和設計顧問。他說，他的記憶體架構採用了光纖通道技術中的一些功能。這種記憶體架構可並行訪問記憶體晶片的存儲單元，打破串列訪問的瓶頸。這種瓶頸阻礙了閃存的應用。這種架構適用於任何記憶體晶片的存儲單元。Ashwood的記憶體架構把單個記憶體晶片上的存儲陣列旁邊的智慧控制器電路集成在一起，提供並行訪問數百個同時進行的流程，從而提高數據吞吐量和降低平均訪問時間。

. X2 ~( |6 y4 H& e; \( v8 hAshwood說，同DDR記憶體相比，他的架構是深入到記憶體晶片內部，重新組織訪問存儲單元的方式，從而更有效地使用這些存儲單元。數據傳輸速度將更快。他說，DDR2記憶體的數據傳輸速度最快為每秒12GB，而其記憶體架構在存儲單元中使用閃存等技術時的數據傳輸速度可達到每秒16GB。
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美國卡耐基-梅隆大學已經證實，Ashwood的記憶體架構確實是記憶體設計的一個突破。
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不過，Ashwood承認，他的記憶體架構還存在兩個缺陷。第一，這個架構仍然只是紙上的設計，目前僅僅完成了軟體模擬。第二，他的架構的並行訪問開銷稍微降低了單個存儲單元的訪問速度，儘管許多並行訪問通道抵消了這個問題。