奇岩電子採用Cadence Encounter RTL Compiler

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協助ASIC晶片tape out並及時上市
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Cadence益華電腦宣布，專精於USB相關產品的晶片與IP設計服務奇岩電子（Moai Electronics），已採用Cadence RTL Compiler，順利推出尺寸更小的消費性電子產品晶片。由於消費型電子產品的上市時程十分重要，而Cadence Encounter RTL Compiler全面性合成功能技術，能縮小消費性電子產品晶片尺寸並加速晶片的上市時間。
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( ~- r9 O3 R  D奇岩電子陳麗娟協理表示，Cadence Encounter RTL Compiler的合成技術與支援，能夠同時充份滿足客戶在成本及上市時間上的需求。除了Encounter RTL Compiler，奇岩也使用Cadence Conformal LEC來驗證晶片設計，使實現流程更流暢，幫助產品能快速成功地推出。
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Encounter RTL Compiler是Encounter數位IC設計平台的一部份，具有提高晶片效能、縮小晶片尺寸、降低耗電量及加快佈局規劃與繞線的強大優勢，協助客戶生產更小、更快、運作溫度更低的晶片，提高客戶的競爭力，更降低整體成本。

0 R2 G) Z0 l6 R3 v; V7 Q  X7 FCadence副總裁徐季平博士指出，奇岩電子此次成功運用Encounter RTL Compiler協助ASIC tape-out，是Cadence全面性合成技術，協助台灣客戶的另一個成功範例。

Encounter RTL Compiler在消費性電子、通訊、電腦、網路、圖形及SoC等高度競爭性產品的設計上，已廣受全球技術領先企業採用，在台灣採用的客戶亦大幅成長，就是因為Cadence能夠幫助客戶在極短的時間內建立出更小、更快及耗電量更低的晶片設計。該公司也期待繼續能幫助更多的客戶，更有效率地產出最佳化的IC設計品質。


% r( s0 M( F  Z' J9 R富士通(Fujitsu)採用Cadence益華電腦Encounter Timing System進行Signoff 時序分析
+ a! ^% O0 x2 yFujitsu Adopts Cadence Encounter Timing System for Signoff Timing Analysis
3 M7 u" U1 A( U( X. \: O% x. eCadence Encounter Timing System Achieves Signoff Qualification for Designs at 90 Nanometer and Below

SAN JOSE, Calif. , September 5, 2006

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Fujitsu Limited has adopted Cadence® Encounter® Timing System (ETS) for timing analysis in their implementation flow. ETS delivers superior signoff timing accuracy, usability and functionality for designs at 90 nanometers and below.

The Encounter Timing System provides full-featured integrated static timing analysis (STA) and signal-integrity (SI) analysis delivering consistency through physical implementation, optimization and timing signoff. ETS builds upon Cadences industry-leading SI signoff solution, Encounter CeltIC® Nanometer Delay Calculator (NDC), and extends to include signoff STA delay calculation, and the popular Encounter-based global timing debug features for quick and easy identification and optimization of timing issues and exceptions.

2 R0 ]9 b7 n; W"After evaluating and testing ETS on multiple production designs, it is clear that ETS will deliver benefit in terms of signoff accuracy, feature set, and productivity," said Satoshi Andou, general manager, Design Platform Development Division, Electronic Devices Business Unit of Fujitsu Limited. "ETS met our timing signoff requirements and we are now incorporating ETS in our ASIC implementation flow. We are also looking forward to extending the collaboration with Cadence toward statistical STA to remove the pessimism in timing imposed from process variation."
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"Cadence and Fujitsu have collaborated for several months to meet timing signoff requirements. We are very pleased that Fujitsu, one of worlds leading ASIC suppliers has chosen to adopt and support the Encounter Timing System for timing signoff," said Wei-Jin Dai, corporate vice president of R&D at Cadence. "With ETS, we now offer Fujitsu a complete system-on-chip platform from netlist to GDSII."