智原科技採用捷碼(Magma)的FineSim SPICE電路模擬器

amatom

"To enable analog designers to deliver the required combination of efficiency, productivity and innovation needed for today's ICs, the analog design process must be accelerated and automated," said Anirudh Devgan, general manager of Magma's Custom Design Business Unit. "By making analog routing fast, predictable and repeatable, Titan improves routing productivity by a factor of 10, allowing designers to achieve their time-to-market and performance goals. Titan should help iWatt solidify its position as one of the most innovative power IC companies in the world."
  B/ J& d6 @; L( S  H& W0 L
Titan: Accelerating Analog Design

Magma's mixed-signal SoC design environment includes the comprehensive Titan Mixed-Signal Design Platform and the Titan Accelerators. The Titan Mixed-Signal Platform is the industry's first true mixed-signal design platform. It integrates implementation and verification while delivering first-time-correct, predictable mixed-signal designs. The Titan mixed-signal platform includes user-friendly full-custom schematic and layout editors, an analog simulation environment and correct-by-design schematic-driven layout.

amatom

Titan Accelerators are advanced technology solutions that dramatically improve analog/mixed-signal design productivity and reuse. Titan Analog Design Accelerator (Titan ADX) is a model-based analog design and optimization tool that enables analog design reuse. ADX creates new designs from Magma's library of FlexCell building blocks, and makes existing designs reusable as FlexCell models. Titan Analog Virtual Prototyper (Titan AVP) is a layout-aware schematic design tool that performs simultaneous electrical and physical co-design for rapid schematic-to-layout convergence. Titan Analog Layout Accelerator (Titan ALX) automates migration of analog cell layouts to new process technologies while preserving design intent. Titan Shape-Based Router (Titan SBR) automates difficult routing tasks improving routing productivity by a factor of 10.
8 g7 {6 K# v9 Y2 w
' X/ ^- h* b# `6 O3 B( m4 ~About iWatt, Inc. ?
: Y' B( e" w8 X+ _) q4 A' H
3 f( M+ _1 |$ Q- o% y4 Z* giWatt, Inc. is a power control IC company that designs, develops and markets semiconductor products for the communication and consumer market segments. The company's patented digital control expertise raises the bar in power supply price/performance metrics. iWatt is currently working with market leaders in the communications, flat panel display, and consumer electronics markets to develop high-density, high-value AC-DC and DC-DC power supplies. iWatt is backed by VantagePoint Venture Partners and Sigma Partners, two leading CleanTech investors, and Horizon Ventures. The Company's Silicon Valley headquarters is located in Los Gatos, CA with additional offices in Taipei, Taiwan; Seoul, Korea; Tokyo, Japan; Shenzhen, China; and Hong Kong. For more information, visit www.iwatt.com

tk02561

Open-Silicon Adopts Magma's SiliconSmart ACE for Standard Cell and I/O Cell Characterization and Modeling to Maximize Performance on Advanced-Node Designs
/ i, q4 ^! c% S: ~* hAccelerated Circuit Engine Fully Automates the Characterization Flow to Provide an Order-of-Magnitude Improvement in Throughput
# Z$ u) R0 e  i$ K, j# ^
0 A( q- Y4 l  S3 `- u+ fSAN JOSE, Calif., Aug. 22, 2011 (GLOBE NEWSWIRE) -- Magma® Design Automation (NasdaqAVA), a provider of chip design software, today announced that Open-Silicon has standardized on SiliconSmart® ACE for standard cell and I/O cell characterization and modeling. A long-time user of SiliconSmart, Open-Silicon upgraded to SiliconSmart ACE to leverage the tool's proven ability to quickly and accurately characterize libraries for multiple process, voltage and temperature (PVT) corners which will enable them to maximize power savings and performance on advanced-node designs. Open-Silicon uses SiliconSmart ACE in particular for characterization of new cells created with its patented CoreMAX™ design-specific library augmentation flow and for library recharacterization for Open-Silicon's VariMAX™ technology with back biasing.
* y- m& H. U: F
" a6 S* w6 O; `"We have used SiliconSmart for several years and our customers have benefitted from its capabilities," said Shrikrishna Mehetre, engineering manager at Open-Silicon. "As we move to more advanced process technology, extracting every picosecond of performance requires fast, accurate characterization of multiple PVT corners. With its superior capabilities and Magma's ongoing world-class support, we have complete confidence in using SiliconSmart ACE for our next-generation designs."
; ?6 H7 k) d$ E( G1 \
"With enhanced accuracy, speed and ease of use, SiliconSmart ACE provides an order-of-magnitude improvement in throughput compared to other solutions," said Anirudh Devgan, general manager of Magma's Custom Design Business Unit. "Its proven ability to significantly reduce time and effort makes SiliconSmart ACE the clear leader in characterization and modeling."
; N$ ]" }9 a% C  V$ x( H& `6 O0 d
SiliconSmart ACE: Order-of-Magnitude Improvement in Throughput
9 \9 ^0 G# A: n4 {
Featuring industry-leading accuracy, throughput and ease of use, SiliconSmart ACE provides standard-cell, I/O, custom macro and memory characterization and modeling for all popular design flows. It supports all the advanced timing, power, noise and statistical modeling specifications. The proprietary Accelerated Circuit Engine (ACE) fully automates the characterization flow, employing the most advanced circuit function recognition technology and vector generation and optimization algorithms to efficiently characterize cells without compromising accuracy. For maximum performance, SiliconSmart ACE embeds Magma's accurate and ultra-fast SPICE simulator, FineSim™ SPICE, providing up to an order-of-magnitude improvement in throughput. It includes a closed-loop model validation flow that allows users to seamlessly launch third-party tools within the Magma system to verify the generated models.

heavy91

Chrontel Standardizes on Magma to Accelerate Development of Analog/Mixed-Signal ICs
Tight Integration of the Titan Analog/Mixed-Signal Design Platform, FineSim Simulation and Quartz DRC/LVS Physical Verification Solutions Delivers 50 Percent Improvement in Productivity

- j" E1 W, @0 p+ pSAN JOSE, Calif., Aug. 22, 2011 (GLOBE NEWSWIRE) -- Magma® Design Automation (NasdaqAVA), a provider of chip design software, today announced Chrontel, a leading provider of display interface ICs for personal computers, portable media players and smartphones, has standardized on the Titan™ Mixed-Signal Design Platform, FineSim™ SPICE and FineSim Pro circuit simulation, and Quartz™ DRC and Quartz LVS physical verification products. Chrontel selected the Magma software after an extensive evaluation and benchmarking of the Titan-based flow against other EDA flows resulted in a 50 percent improvement in productivity.

6 _, T# V- X# P5 I0 I' M"To keep up with the changing demands of the consumer market, our customers need a constant supply of innovative visual interface IC solutions," said Dr. David Soo, president and CEO of Chrontel. "Magma's comprehensive, highly integrated analog/mixed-signal design platform and simulation and verification solutions streamline our entire analog/mixed-signal design flow and allows us to deliver the high-quality, differentiated silicon our customers need — on time."

/ z7 J  s% q. ?"With the tight integration of Titan, FineSim and Quartz, analog designers can leverage faster throughput, higher capacity and more automation to develop innovative analog/mixed-signal ICs faster and more cost effectively," said Anirudh Devgan, general manager of Magma's Custom Design Business Unit. "Chrontel's decision to standardize on the Titan-based flow illustrates how Magma's Silicon One initiative brings together superior technology, design expertise and our customers' creativity to deliver profit-driving differentiated silicon."
: l; P( M' q0 X3 e- r
Silicon One Solution for Analog/Mixed-Signal Design

With Titan, FineSim and Quartz, Magma's Silicon One solution for analog/mixed-signal designs provides the highest speed, capacity, and the required accuracy to be able to handle even the largest analog/mixed-signal SoC designs. It includes Titan, a breakthrough analog automation and optimization product that is fully integrated into Magma's Talus® digital implementation platform. The Titan platform delivers first-time-correct, predictable mixed-signal designs, without sacrificing performance, and shortens the design process by weeks. With automated mixed-signal assembly and verification, Titan provides an order-of-magnitude productivity improvement over other tool flows. FineSim provides fast, high-capacity circuit simulation that can be deployed for MCU, FPGA, interface and power management chips to fully simulate and verify these designs. The fully scalable Quartz DRC and Quartz LVS provide a superior alternative to traditional tools, allowing designers to handle more complex designs in less time with existing hardware.

jcase

智原科技發表完整的聯電28奈米元件庫與記憶體編譯器
7 a8 q+ ]1 `% U- ~多項專利技術，滿足最佳效能、最小晶片尺寸，提升產製良率
: A3 S* i" Q% i0 Q! T: Y
3 J! W9 A& {9 i% Z$ W+ o2 {' @0 Z[台灣 新竹] 2014年4月16日

& Y3 z; [; \8 x( l$ I' {1 f! RASIC設計服務暨IP研發銷售領導廠商 ─ 智原科技（Faraday Technology, TAIEX: 3035）於今日發表在聯電28奈米HPM（High Performance for Mobile，高效能行動運算）與HLP（High-Performance Low Power，高效能低功耗）製程的元件庫（cell library）與記憶體編譯器（memory compiler）。這套完整的28奈米解決方案，可滿足市場對低功耗、高密度與高速效能的需求，並有效提高良率。完成迄今，已經受到客戶的高度肯定與採用。
1 V6 ]; D3 W/ k, T& }
6 ~- P+ x" t4 ^* K7 r因應不同市場的需求，智原科技的28奈米元件庫中，包含了7軌的miniLib™ 、9軌的通用型元件庫、以及12軌的UHS-Lib™。同時，全系列都搭載了PowerSlash、多種臨界電壓元件、不同通道長度元件（multi-channel length）等低功耗機制。當中，miniLib™在不影響繞線能力（routability）的情況下，可大幅縮小晶片面積，約達20%；而12軌的UHS-Lib™則可提高ARM CPU的效能，達到1.5GHz。

jcase

為了克服先進製程中的高度變異性，智原的28奈米記憶體編譯器，採用多種輔助電路來提高產出的良率與效能。其中，智原專利的NBL（Negative BitLine）技術可在低壓狀況下，強化寫入的能力，且經矽驗證，可在28奈米HPM變異最大（worst corner）的製程條件下，提升良率。而新一代的感測電壓追蹤技術（tracking control scheme of sensing margin）與DPRAM的儲存單元電流增強技術（cell current boost）可增加讀取成功率，降低最低工作電壓約200mV。另一項獲得專利的WLUD（Word-Line Under-Drive）技術，在測試晶片上，也已經被證實可有效降低讀取干擾（read-disturbance）。而ROM的部分，智原則採用最新的字元線漏電控制（bit-line leakage suppression），與隨製程變化自動調整的位元線升壓（adaptive word-line boost）技術，進一步擴大低壓條件下的讀取範圍。

- z' W8 b. m) i智原科技資深研發處長陳治弘表示：「奠基於二十年以上，與聯電合作開發基礎元件IP的經驗，智原科技已經具備相當深厚的技術實力、以及對聯電製程的高度掌握和熟悉度。所以在每一世代所推出的IP，不論是在尺寸、效能、功耗、以及良率表現上，都能具備高度競爭力，吸引IP與ASIC客戶的採用。同樣地，對於新推出的28奈米解決方案，我們也有相當的信心，可持續協助客戶在市場上攫取更大商機與獲得成功。」