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[問題求助] Clock Isolation Logic and Circuit for Complex SoC Designs

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發表於 2006-11-12 09:46:21 | 顯示全部樓層 |閱讀模式
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這段英文講的是「時鐘隔離」技術。把時鐘作為資料處理時遇到的問題以及相關的解決方法!
哪位高手能幫忙翻譯一下大意?能有進一步評介、討論分享更好!? :o

Complex SoC designs often implemented various IPs and embedded memories. It is not uncommon that clocks are used as data to qualify signals in IPs, particularly legacy ones, and to switch address and data buses in dual access embedded memories which are popular in low-power designs. Using clock as data has created various issues in timing closure, particularly in logic and physical synthesis. To resolve the issue, a novel clock isolation method has been developed. The principle of the method is to introduce a clock isolation circuit which tracks clock transitions just like a clock signal, yet isolates the clock from the “clock-used-as-data” logic. As the result, clocks will not be part of logic paths and the design becomes “STA-friendly” where all path timing can be checked by synthesis and STA tools in normal ways. The advantages of the method include better quality-of-result of a design, fewer timing closure iterations and less complex design flow. The clock isolation method has been successfully implemented and verified in a complex SoC design.

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嗯..我翻看看...不對的地方,請大大們多多指教~~ Complex SoC designs often implemented various IPs and embedded memories. 多工SOC 設計經常被應用在不同IPS和崁入式記憶體 It is not uncommon that clocks are used as data to qualify signals in IPs, particularly legacy ones, and to switch address and data buses in dual access embedded memories which are popular in low-power designs. 尤其在本身,時鍾被作為 ...
發表於 2006-11-12 09:46:22 | 顯示全部樓層
嗯..我翻看看...不對的地方,請大大們多多指教~~

Complex SoC designs often implemented various IPs and embedded memories.
多工SOC 設計經常被應用在不同IPS和崁入式記憶體
It is not uncommon that clocks are used as data to qualify signals in IPs, particularly legacy ones, and to switch address and data buses in dual access embedded memories which are popular in low-power designs.
尤其在本身,時鍾被作為資料限制IPs的訊號並不是普遍,而雙通道崁入式記體做切換位址和資料匯流排在低電源設計是較普遍。
Using clock as data has created various issues in timing closure, particularly in logic and physical synthesis.
使用時鐘作為資料在定時關閉已經創造各式各樣的問題,特別在邏輯和物理綜合。
To resolve the issue, a novel clock isolation method has been developed.
為解決此問題,開發出新的時鐘隔離方式。
The principle of the method is to introduce a clock isolation circuit which tracks clock transitions just like a clock signal, yet isolates the clock from the “clock-used-as-data” logic.
主要的方式是導入時鍾隔離電路追蹤時鍾轉換如時鍾訊號,然後"時鍾做為資料"邏輯做為隔離時鍾技術。
As the result, clocks will not be part of logic paths and the design becomes “STA-friendly” where all path timing can be checked by synthesis and STA tools in normal ways.
依這項技術,在正常的方式透過綜合及STA 工具所有通路會被檢查,時鍾將不會是邏輯通路的一部份且此設計會變成"STA-friendly"。
The advantages of the method include better quality-of-result of a design, fewer timing closure iterations and less complex design flow.
這個方法的優勢含括更好成果品質設計、較少定時關閉重覆和減少複雜設計流程。
The clock isolation method has been successfully implemented and verified in a complex SoC design.
時鐘隔離方法在多工SOC設計上已經成功實行且被證實。
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