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AMD Geode LX 800@0.9W處理器
General Features+ O2 \$ I2 E, s# y; J$ @
■ Functional blocks include:
; L9 L; n. S+ ]- B5 j9 s1 F— CPU Core9 i( S' U& {' F6 D7 J+ E
— GeodeLink™ Control Processor/ j. k& t g4 O; N/ p
— GeodeLink Interface Units& Q# Z6 S4 S( M: A7 d# r @2 N
— GeodeLink Memory Controller
9 b$ j6 E, `) }" m. \6 S— Graphics Processor7 G+ m; O0 N- c! D5 U/ K" Y
— Display Controller& y. Q9 W+ z2 {. e t% R9 P8 E) O
— Video Processor( B) F6 G2 A% L% c. d
– TFT Controller/Video Output Port
* h* Q9 g( P& S9 e& g— Video Input Port. \" \! F$ I9 N9 g7 f$ f7 w4 T
— GeodeLink PCI Bridge7 x# x+ E1 u/ q- m* F3 a3 \
— Security Block7 y( `1 e0 A% _. o1 @: s
■ 0.13 micron process
7 g& ], {$ y1 `/ `■ Packaging:
9 n5 p2 A( ^* L& E1 I— 481-Terminal BGU (Ball Grid Array Cavity Up) with
5 s% i' a- F$ [" ointernal heatspreader+ x2 l2 g: v, D
■ Single packaging option supports all features
0 x Q m% Z& O2 _8 O1 f) }CPU Processor Features
) {- h. i# C6 z5 ?/ t■ x86/x87-compatible CPU core/ g1 ]# a2 _* q2 G
■ Performance:" M* F! U9 z8 `3 d& l) B
— Processor frequency: up to 500 MHz: |) A* i0 g7 i; k$ G) y
— Dhrystone 2.1 MIPs: 150 to 4504 {. K" V( Z p- ^1 {5 b; }+ m
— Fully pipelined FPU
7 ~5 [8 l. d* [$ H1 c. M# _. Q■ Split I/D cache/TLB (Translation Look-aside Buffer):' B4 h8 }: E! o+ O$ t
— 64 KB I-cache/64 KB D-cache
- @6 A: G$ Q' F- z3 X— 128 KB L2 cache configurable as I-cache, D-cache,
/ A2 l! O+ P8 U) b/ b1 }" Nor both1 J; t4 ^! X3 `( U2 R' \
■ Efficient prefetch and branch prediction) ?* e( Y" C: h& l4 I
■ Integrated FPU that supports the MMX® and) Z" W" }! p/ ^6 @4 i0 e K
AMD 3DNow!™ instruction sets
; L, B3 w: k* y- C1 c& A■ Fully pipelined single precision FPU hardware with
9 `+ E. }* P' Q' |/ K6 Nmicrocode support for higher precisions& V5 E) w; v' D: P& _
GeodeLink™ Control Processor
4 ~' m' k& u q8 o. e" N/ k: _■ JTAG interface:
8 i& t! Q, ~ x1 v/ n— ATPG, Full Scan, BIST on all arrays
+ \- g/ H+ V4 \3 s- v, x— 1149.1 Boundary Scan compliant
5 r, I( w7 U- V■ ICE (in-circuit emulator) interface( `* U5 y' [8 {) A) _3 R
■ Reset and clock control
* M" t+ e+ ^- Q5 u C0 F0 W■ Designed for improved software debug methods and, d0 |7 [. g9 ]; L3 N
performance analysis
* G$ g, H! S" f6 A" @/ h■ Power Management:" z# D1 J$ f* W8 B( D" B- S
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @/ U/ C4 _$ s- E/ N5 Y! A, E
500 MHz max power
. y6 |5 }, z% l( Z— GeodeLink active hardware power management
2 `! x5 V/ P+ w) @4 k' k— Hardware support for standard ACPI software power6 d7 D1 ]' j0 r* u6 n$ u7 v D- V9 e$ C
management! a! C9 I7 h/ S+ N' m
— I/O companion SUSP/SUSPA power controls/ `! |' ]% V9 A! z3 ^3 E- Z
— Lower power I/O3 g8 C2 V/ h0 J5 g/ @* O
— Wakeup on SMI/INTR5 v/ M1 u) F) [* Q" k( s1 D
■ Designed to work in conjunction with the3 J" i7 s! c8 K v" D
AMD Geode™ CS5536 companion device0 j. @3 ? g, G% T: j( R
GeodeLink™ Architecture
$ ^- E3 z* o/ V4 ?* j■ High bandwidth packetized uni-directional bus for
0 v1 {7 x* ^0 `) U3 r0 m! minternal peripherals
4 O$ f- W, V/ T3 c1 w# B4 U7 i■ Standardized protocol to allow variants of products to be
& `% P: \. b- }/ E# Gdeveloped by adding or removing modules
; {* h. W6 B6 v2 P R4 `■ GeodeLink Control Processor (GLCP) for diagnostics# f; `! Y, x1 b9 B, ?
and scan control0 y& E% F3 | n2 m8 X' U" C
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect( ~; i5 A, g- J* T
GeodeLink™ Memory Controller
; v0 _3 i! I- e. @& x■ Integrated memory controller for low latency to CPU and# \" U9 F/ o2 P* e) t8 {: X5 |1 o1 r
on-chip peripherals% J' e' j% V) L4 }% G% G
■ 64-bit wide DDR SDRAM bus operating frequency:
1 T M. |2 Y; t— 200 MHz, 400 MT/S
5 z* _& L# H. [- u$ }! l& W■ Supports unbuffered DDR DIMMS using up to 1 GB
8 _/ {2 Z! f' }( eDRAM technology3 J- [6 }9 z9 U5 v7 o
■ Supports up to 2 DIMMS (16 devices max)& @$ L: s: \9 h. B
2D Graphics Processor# _5 F, @9 v, d/ Y
■ High performance 2D graphics controller4 `; U+ i) Z' L0 ?0 K. n1 I
■ Alpha BLT
5 C0 \2 k7 E% C& A■ Microsoft® Windows® GDI GUI acceleration:
: D5 {. T- G7 t— Hardware support for all Microsoft RDP codes
, H7 c n5 {8 S8 f ?. H■ Command buffer interface for asynchronous BLTs
9 x1 a5 `* E8 B7 D■ Second pattern channel support7 y) }9 U' P$ |
■ Hardware screen rotation |
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發表於 2007-2-6 18:17:18
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