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AMD Geode LX 800@0.9W處理器
General Features
`, | u" e! X$ R: k, c■ Functional blocks include:
4 q: G3 a" K0 F1 Q# w9 R: f! m1 S. E1 {— CPU Core4 @. h; n3 B* x- m9 i! G4 H
— GeodeLink™ Control Processor3 Y6 y* Y, U' n1 \0 _7 S5 M- R
— GeodeLink Interface Units M0 ]: _/ J) M/ c3 q# i. D: O# O
— GeodeLink Memory Controller4 Y/ N6 P1 t) E0 a1 m
— Graphics Processor
1 F3 L3 L2 h' l— Display Controller9 }8 x/ l: y5 E4 M% q5 S8 l3 ?
— Video Processor
' U4 {9 Q5 M# t& q– TFT Controller/Video Output Port
0 W& V% z6 P$ P0 ?+ y" f; i— Video Input Port8 p7 s3 Q" b/ Q* |' Y
— GeodeLink PCI Bridge) ^$ t/ I# y9 a. }3 Z
— Security Block
6 Z3 S! Y3 |- x, C; p■ 0.13 micron process/ [- S0 @1 r/ H, i
■ Packaging:. a; M5 Q7 K" q2 N
— 481-Terminal BGU (Ball Grid Array Cavity Up) with8 K! V( `$ _/ S. d) z
internal heatspreader' @' R8 C5 b; M9 y2 j# S
■ Single packaging option supports all features
* l4 S! M/ |. i/ ?. G. a& PCPU Processor Features0 ~0 S# G, R, B0 i+ V
■ x86/x87-compatible CPU core
' I5 D7 [ |. O$ L0 y■ Performance:" N! z9 f/ X" v! |" h, s
— Processor frequency: up to 500 MHz
% |3 ]' @# Q2 O. U1 l+ l+ t— Dhrystone 2.1 MIPs: 150 to 450
; l7 ?- Z/ ^; A8 ]$ c— Fully pipelined FPU
9 f+ i6 B* l* S1 Z! P/ h- \) G■ Split I/D cache/TLB (Translation Look-aside Buffer):
" h+ J7 D& C3 _% n# z— 64 KB I-cache/64 KB D-cache
& `: H! K1 M1 d G9 X— 128 KB L2 cache configurable as I-cache, D-cache,
6 d$ b2 r! F( k1 Q/ Por both
6 ?- Q! y7 C8 U: M( I- x■ Efficient prefetch and branch prediction
4 j; E' j, R8 @) Q■ Integrated FPU that supports the MMX® and
7 w4 |, J; [; K; c" {AMD 3DNow!™ instruction sets
* C% {$ o" [+ S# x; [■ Fully pipelined single precision FPU hardware with6 u5 @9 i+ h3 J5 U# q6 f) u
microcode support for higher precisions) J( W3 \* l& \$ |' K
GeodeLink™ Control Processor
: F+ n! O. i/ M* g) X& O& V4 F■ JTAG interface:+ Q! V& l0 L/ i7 @) y3 O Q2 g
— ATPG, Full Scan, BIST on all arrays+ Y- {2 s$ | t
— 1149.1 Boundary Scan compliant
; C- Q6 q4 ^' f7 S: u2 ]% B■ ICE (in-circuit emulator) interface- |/ V- g/ p, O7 k5 L
■ Reset and clock control
$ f3 |( D4 ^$ D1 G■ Designed for improved software debug methods and
) a8 J4 ?( T2 ]" \performance analysis+ ^$ N6 j0 c3 ~0 J& t/ ~
■ Power Management:
. O- q9 M/ q% F; X1 j5 D— Total Dissipated Power (TDP) 3.8W, 1.6W typical @1 [/ [2 {8 |5 b' t5 S) n- k
500 MHz max power
7 O, d' x8 H; u R/ m" l4 C2 z— GeodeLink active hardware power management% q3 A1 ]; o8 k$ {, T2 T
— Hardware support for standard ACPI software power" y! q% y; k3 \6 v l" E
management6 n$ z0 c1 h& ~1 i0 v6 N: b9 s
— I/O companion SUSP/SUSPA power controls( W# N4 q8 @/ H# G0 K, x
— Lower power I/O
0 ~) W: I9 p" Y% m8 `# W$ K— Wakeup on SMI/INTR
n% f: i e0 s1 M/ [! l■ Designed to work in conjunction with the9 Z u* d$ |7 H2 h5 S/ G4 i
AMD Geode™ CS5536 companion device' @0 ^5 t( p7 t7 U% E$ N/ B4 V9 X! e
GeodeLink™ Architecture2 d7 @* L& S9 N' N9 i
■ High bandwidth packetized uni-directional bus for4 }4 I. k4 m% `% r# ?
internal peripherals4 q* R) Y& F! D9 R4 `( C* H: q! b
■ Standardized protocol to allow variants of products to be) }5 N( k5 D# O7 c9 y
developed by adding or removing modules
' R5 e j2 h3 u& w' M■ GeodeLink Control Processor (GLCP) for diagnostics9 ]/ I! I8 q [% B3 \
and scan control: d+ I& ]) h. g {( @
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect, {# x# M6 K6 P b6 O1 r
GeodeLink™ Memory Controller$ w; ?8 p4 w6 W+ f
■ Integrated memory controller for low latency to CPU and: x6 u" ?5 C8 Y) y- H( ^ `3 {
on-chip peripherals) \! g' C2 g9 i. Q
■ 64-bit wide DDR SDRAM bus operating frequency:
+ I. ^8 O/ e+ Q. x5 U2 C( J— 200 MHz, 400 MT/S
4 z% M8 {) m3 g0 q: G■ Supports unbuffered DDR DIMMS using up to 1 GB
0 ]1 g* z) `1 D$ oDRAM technology
% v, s6 @9 b/ B5 m( {■ Supports up to 2 DIMMS (16 devices max)7 J3 m$ V; b* h' X
2D Graphics Processor* E* R) o" W% _( L( W1 F# T
■ High performance 2D graphics controller
- }6 {( z' g7 b1 @3 ^9 M■ Alpha BLT- S, G0 k* u7 e9 @
■ Microsoft® Windows® GDI GUI acceleration:/ J* I& a& H$ I( C7 g
— Hardware support for all Microsoft RDP codes/ \1 j" W- T2 T& Y! X1 R% b* I
■ Command buffer interface for asynchronous BLTs
: g8 `4 C, [7 F, e4 V■ Second pattern channel support% k0 T6 b5 d; S
■ Hardware screen rotation |
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發表於 2007-2-6 18:17:18
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