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0. Check circuit topology and connectivity.0 R& M/ x) M! U+ ^8 V* ~" `9 d
This item is the same as item 0 in the DC analysis.
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- H0 L( m" a0 |0 X/ j8 I8 J5 s0 O% D1. Set RELTOL=.01 in the .OPTIONS statement.
/ f3 j& ^+ t1 T mExample: .OPTIONS RELTOL=.01. v4 A, Y( A. Y b, _
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2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
( D/ I% b& L5 w$ C9 mExample: . OPTION ABSTOL=1N VNTOL=1M; Y7 p% t e1 V5 |6 e9 E( Q
, H& U* G, K2 r! _% \" _4 h" i0 H3. Set ITL4=500 in the .OPTIONS statement.2 U9 }3 W( S6 H
Example: .OPTIONS ITL4=5008 g- n+ q# f% x9 U- |- G, ~7 ~" o% v
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4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.& I2 o- L v- ?# N
' a7 f# V' o! v- f5 _5. Reduce the rise/fall times of the PULSE sources.' x# ]9 R5 j t% L# d
Example: VCC 1 0 PULSE 0 1 0 0 09 b# M$ F8 a" M3 [
becomes VCC 1 0 PULSE 0 1 0 1U 1U) k: D7 y0 }/ n1 A N6 f% j
& D9 h' q' a3 F& j* {* \& i* h# Y6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources." f* C3 Y$ ]9 v6 L& Q5 E3 A" m; s
Example: .OPTIONS RAMPTIME=10NS. `2 q' |: h! F5 _" U W$ s0 d8 b% J3 g
( H- t8 B9 L3 ~" I7. Add UIC (Use Initial Conditions) to the .TRAN line.
! C+ ?8 S9 p2 G# P' g4 fExample: .TRAN .1N 100N UIC
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! ?! J2 E( m& ~; B8. Change the integration method to Gear (See also Special Cases below).; n* a; j3 A, M6 T/ m0 w3 b+ I$ ~
Example: .OPTIONS METHOD=GEAR |
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