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0. Check circuit topology and connectivity." n* |- r I" i9 u9 T
This item is the same as item 0 in the DC analysis.
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1. Set RELTOL=.01 in the .OPTIONS statement." U3 Q o8 N. ~# S9 I& \' v% X
Example: .OPTIONS RELTOL=.012 n+ |- F* R) m) j' y- E, ?2 v x) g
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2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.. e/ ~) K1 a7 N0 w9 {( R. L
Example: . OPTION ABSTOL=1N VNTOL=1M% m R8 Q$ I" X1 i/ v# X; @
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3. Set ITL4=500 in the .OPTIONS statement.
( j3 Q0 x& Q& VExample: .OPTIONS ITL4=500/ B8 s0 D( b p& m3 y" m
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4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.
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$ |0 U+ _* c& ?3 y5. Reduce the rise/fall times of the PULSE sources.
! E1 T1 e4 X, h7 T1 _5 T; m9 SExample: VCC 1 0 PULSE 0 1 0 0 0
. ^( Q5 d( L2 A" q2 l) \7 b4 |2 J! tbecomes VCC 1 0 PULSE 0 1 0 1U 1U! [" S1 o& G; D2 v# m% g
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6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.8 L4 C1 c; p! ?9 [
Example: .OPTIONS RAMPTIME=10NS
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7. Add UIC (Use Initial Conditions) to the .TRAN line.
6 B& q$ E* P( s" f1 f1 X kExample: .TRAN .1N 100N UIC
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8 x" }1 ?/ t1 J* F3 u8. Change the integration method to Gear (See also Special Cases below).
3 x( N9 A( u- Q: p( Q3 r3 `Example: .OPTIONS METHOD=GEAR |
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