|
Junior Physical Design Engineer2 Z- n1 Q' Z/ _9 ^: ]) [# M0 ^
, t# ^& r& j0 l+ } S4 A( P公 司: famous IC company6 e! g0 e' `, x. R' S& Y C
工作地点:北京! V' {3 t6 |7 S* J: A
# J, J& J% O; T' k" mPosition Tasks, Duties and Responsibilities _ }& J# E# q* z
The ASIC Physical Design Engineer will:
2 ?5 n* y w$ e- Q9 u! \& X Complete third party IP integration and ensure vendor guidelines are followed.
/ p& j, |+ n' P) f% @ Responsible for physical verification (DRC/LVS). - w* H n# B% K% \8 Q7 ~
IO ring design, fullchip floorplan. & E2 y; v* T( D8 r
Block level implementation.
, v E" Y$ f, C3 c; F Work with front-end engineers to resolve problems and achieve design closure.
" X3 |" V/ o9 ^+ {. M3 v# _' E* n. \8 M+ Q) p4 ^* H2 t2 z
Candidate Qualifications: * J3 L9 ^; X6 u" j
Candidate must:
: l' v* U9 ~1 h2 I' f/ I f$ y, M Hold BSEE (MS preferred). . `; @# r# R: S+ u% [
Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification ' f/ _- \# z0 f; A
Be able to complete block and chip level tapeout quality LVS and LVS and DRC. [% _6 @2 N3 e, ?/ L% ]
Have the ability to independently identify and resolve design, tool, and flow problems. ( g- b a- D' F" g4 o& f' b$ _
Have related timing and physical concept. B( `, \. \: N1 `1 y
Be able to design and implement physical design strategies and methodologies for deep submicron designs.
! u. y& t; R- F! t, ~8 ? Familiar with EDA tools.
) H) g* g4 n6 z; y Familiar with Linux environments.
4 y% l# C4 z$ d J! `+ {: b+ y, V7 W# ~4 V8 `7 g- f
Any of the following is beneficial:
2 V9 c* S ^1 V STA constraint design
" n# a2 D+ L" ^) g Equivalence checking ?RTL to gates, and gates to gates. |
|