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Junior Physical Design Engineer, g9 d8 k8 [2 [$ i6 u H
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公 司:A famous IC company
$ T' O' N5 q, L0 D$ u. j工作地点:北京
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7 X2 C% Z% V# r+ Z: @Position Tasks, Duties and Responsibilities
1 Q8 f# h. }1 k$ v- @" Q, p/ k7 xThe ASIC Physical Design Engineer will:
- V$ u& y4 u9 A9 p8 v Complete third party IP integration and ensure vendor guidelines are followed.
, H9 i8 }* N. l Responsible for physical verification (DRC/LVS). 4 {9 p* [) e8 Y) H' B. W
IO ring design, fullchip floorplan.
+ O5 f' O) C# Z Block level implementation. 9 p8 c" M' U' C8 D, \
Work with front-end engineers to resolve problems and achieve design closure. * u/ ]( V1 P4 ~5 M1 i( ^0 @
0 ~+ a$ N, M7 B% s9 ~; ~Candidate Qualifications:
8 \) G7 X% q/ c# r& _Candidate must:
0 g7 t, l4 O. M, } Hold BSEE (MS preferred).
% Q0 P& n+ K! ~ Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
3 |+ W) [+ P- n: C* i' j1 N Be able to complete block and chip level tapeout quality LVS and LVS and DRC. 6 n3 M7 T" r9 M: y% z5 _
Have the ability to independently identify and resolve design, tool, and flow problems. + u8 }& t. U7 x$ ]# w, O
Have related timing and physical concept. ; j& _) t# Q; p; E/ g
Be able to design and implement physical design strategies and methodologies for deep submicron designs., ^% a/ S* N( t; i9 {9 P
Familiar with EDA tools. $ }+ Y) b! a5 b1 \9 D! L( f) ?* u
Familiar with Linux environments. - {; b6 [1 m$ R$ W/ j
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Any of the following is beneficial: 9 n7 l1 S& X; ?( p$ ~0 U7 b3 d# c% p
STA constraint design
: d3 W3 v9 Y3 H% E3 v2 P, ~ Equivalence checking ?RTL to gates, and gates to gates. |
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