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Senior ASIC engineer
客户 a start up company with innovative technology
' V9 i, q6 W. R6 ^地点 Shanghai3 B. M& n- R K' x7 P( a
. S9 x) L, R- P# ?职位要求
5 S( p: `" a9 L, N' k5 + years experience in ASIC design -> must
5 @. A9 N" j, Y% c a6 _* h· MS in Electrical Engineering (or equivalent) is a must have
5 U; h8 O3 {3 g3 [! |- L, G1 Q· Experience with WIFI baseband/MAC or related wireless baseband technology desired -> plus% W0 M+ g% \. a$ o( M
· System on Chip (SOC) Integration Experience, including AHB/AXI, CPU integration -> plus
0 \- f* g( S8 a. F8 i& {* e/ X2 f· Experience with interfaces such as SPI, SDIO, USB -> plus8 Q! H- p9 H; [7 h5 l- {
· Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11 -> plus
5 V) M8 `, c/ A9 I3 @' r· Must be expert in Verilog RTL language -> must+ h' N6 K* u- g! {3 S4 L- [
· Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow. -> must$ y; P1 r7 v& ^
· Verification experience – Verilog, System-Verilog, Coverage Analysis -> must for verification engineer, plus for design engineer, \, w4 c# b) p
· FPGA emulation experience -> plus" c w% P# n+ A% D3 N/ I; F4 m; q
· Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging -> plus
! |) | \ |! D& l' W9 r9 Y· Experience with digital backend |
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