|
Junior Physical Design Engineer4 O* Q: B- x* |) ]5 Y, m t9 \
2 ^2 |( q7 W1 D$ U4 o4 X u# ]公 司:A famous IC company; v/ W0 ^7 F) n* |/ D5 \/ \3 A" I; J
工作地点:北京
5 N' N* v9 B6 \' K, E, B3 ?8 O& m U+ N2 b& I' q
Position Tasks, Duties and Responsibilities ! [! `% \8 v$ W7 {! Y; x1 |
The ASIC Physical Design Engineer will: $ q& _$ |. l% S& S" A
Complete third party IP integration and ensure vendor guidelines are followed.
, Q4 V, K& B7 c8 y$ m% I Responsible for physical verification (DRC/LVS).
+ H% O* S3 q& c IO ring design, fullchip floorplan.
# r) R" V! b- Z0 y/ @ Block level implementation.
/ m7 Y5 ^% k2 D3 ]8 U3 [ Work with front-end engineers to resolve problems and achieve design closure.
l* l1 X3 q8 R8 f! J4 D3 E* I* n$ I7 s! `
Candidate Qualifications:
! ^! C+ O' m: u; M4 B( {, i7 C0 TCandidate must: 5 j! j4 o8 L+ ~5 `2 C- Q& W7 t
Hold BSEE (MS preferred).
8 c5 r% y& \9 }9 w8 z& s4 d% U Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification - l2 ^$ |/ F ^7 ]6 ^3 n
Be able to complete block and chip level tapeout quality LVS and LVS and DRC. ; P7 }3 A1 r3 `, S6 K' `' r" I
Have the ability to independently identify and resolve design, tool, and flow problems.
1 h0 V" ] c' R6 l' l Have related timing and physical concept.
6 b- T! m* s5 ?* O Be able to design and implement physical design strategies and methodologies for deep submicron designs. g. _# C- r* z8 \( q/ w4 ^. K
Familiar with EDA tools. & A/ f M0 o- S/ ?( U, \
Familiar with Linux environments. 2 q* h! D! H8 p! ~2 o
) u) y6 Z; l: @5 F( i1 r* f
Any of the following is beneficial: 1 ~+ u/ a4 @, q) Q5 N) R, q* f2 u, \' m
STA constraint design ) l6 `- v) ^" p0 X
Equivalence checking ?RTL to gates, and gates to gates. |
|