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DIP Application Engineer! ~7 A, S, n1 @ }& i1 R0 m
公 司：One world top EDA company$ h B& R+ B' E8 C' _, C
工作地点：上海/ m+ c3 ~1 j5 M T
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Responsibilities: 0 {; B. ^/ `& ~0 `
1) Providing direct technical support to customers in presale stage to persuade customers to adopt Cadence Design IP solutions for their applications2 K- ]3 k1 r9 _5 ~( W
2) Interface with customer architects and Design IP business unit to enable evaluation of application specific IP performance and features per customer’s SOC requirements.$ H# r: [, L3 N/ A& J) W& M7 S. P
2) Working with the sales team to manage the IP activities in the region to achieve a high customer satisfaction rate and for building strong customer relationships5 y8 _# b7 k2 }: h1 T
3) Providing customer feedback on new/existing requirements for Design IP usage from customers to the IP business unit.; e: B5 }" Z- v- q3 ]4 F
4) Providing direct technical customer support and assistance to enable customers to successfully integrate/use Design IP in their SOC.2 i7 Q, t1 [& Y% C4 `
5) Writing application notes in situation to facilitate customer usage of the IP v4 Z: h( m/ b0 R9 H
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Position Requirements :
/ ^1 A3 |7 }- X1) Experience in digital/analog design and implementation of controllers/phy + c6 v C$ f% d' D6 d+ W; Y
2) Knowledge of serdes and backend implementation is a plus
) f4 i5 f' Z+ j6 k+ A! k+ `3) Experience with SOC architecture include on-chip fabric (AMBA/Sonics OCP/Arteris NOC), external interconnect protocols (e.g PCIe/Ethernet) and DRAM memory protocols (DDRn, LPDDRn), DRAM PHYs, .NAND Flash (Async, ONFI, Toggle NAND), eMMC/SD, MIPI
- f2 ` W+ W2 v; A; \* }+ Q4) Knowing serdes/analog IP is a plus
1 V7 p: `3 y: C7 T9 [4 f, m) V* _5) Exposure to IP-based SOC design flow and real tape-out experience. # ]& x" q2 V m/ w# g/ z9 j1 O
6) Good written and verbal communication skills and problem solving skills are required.
2 ~, U/ `" s& |7 c7) Ability to conduct technical meetings, presentations, seminars and training to customers and to the sales team! e. B0 u% y! s: k3 {$ D* i' B8 U$ M
8) Travel within AP region may be required. 6 K/ _5 z2 p7 I7 g
9) Good understanding of the semiconductor IP marketplace and ecosystem is a plus. |
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IP卡
狗仔卡
發表於 2013-7-23 14:15:33
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