危機就是轉機？類比IC廠逆勢擴大徵求IC設計人才？你覺得去哪家最好？

ranica

Product Engineer -QA
7 r- C  q: |! Y3 F* ~公      司：A famous IC company
4 x. T  P$ k* D: n8 s8 C9 I工作地点：上海

9 f' {% ?' s, bPosition Summary:
Essential Job Functions/Accountabilities:
6 F) K% ^" d2 A3 z5 l9 E: bWork closely with RD and PE team to  
  Q+ }6 s6 r) ]Make sure product (software) quality
QA system maintain and improvement
7 O$ [' M$ f5 z7 nDaily build and daily regression test
0 G: F* ^6 b. h" uProject management and risk control
Bug/enhancements verification and testing
7 R4 Z5 Z* x/ u, `1 w% [) P, p# R6 BProduct release and documentation

5 M2 L# a7 B: S; b" p6 }Minimum Requirements/Qualifications:
Strong scripting skill, Perl/TCL and LINUX shell required
9 q& q& n! J9 t5 x: |( h  F/ U+ {, \Experience of SPICE-based(HSPICE/Spectre/Eldo) circuit simulation
: i4 X& @6 l9 W$ p6 k6 [0 GExperience of package and PCB modeling and simulation with field solvers
Knowledge of High-Speed I/O (DDR) power and signal integrity analysis
Knowledge on die and IO ring physical design, LEF/DEF/GDS is a plus
B.S. in Electrical Engineering or other related areas, 3 years of experience
M.S. or Ph.D. in Electrical Engineering or other related areas, 1 years of  experience, or equivalent combination of education and experience
0 ?4 ]# A- k+ s  h  f0 _Self motivation, teamwork and strong English communication skills ( both written and oral )

ranica

Sr. Software Engineer-电路仿真和建模

公      司：A famous IC company
工作地点：上海
( T1 T. R% u* n% v( s" t
Position Summary:  
Software development and product engineering for power and signal integrity analysis and modeling
Essential Job Functions/Accountabilities:
4 B5 m; h: G) S" UMaintain the IC-package power and signal integrity modeling software, conduct bug fixing and enhancements; develop new features to expand the application and improve the accuracy, capacity and speed; perform development level testings and work with application engineering team to resolve customer issues;

3 i7 f0 I' G% a$ r) SMinimum Requirements/Qualifications:
; M; x2 c5 t2 p- y/ [Strong experience in software development using C/C++
Strong working knowledge in linear and non-linear electric circuit network analysis and modeling
. L& `- @# W2 MKnowledge ofSPICE simulation, or on-die and package extraction is a plus
4 b, q5 }% s1 W) Q* x+ VExcellent communication (both written and verbal) skills in English
' L5 I: r& a5 ?! gMS, Ph.D. in Electrical Engineering, Computer Science, Physics/Math or related fields

ranica

Product Engineer
, M9 H0 t  U$ G) m+ @; n! {9 S公      司：A famous IC company
0 h1 ]' s' P* n: F2 T% l& u" U工作地点：上海
" ~1 [( G$ N* E: ~8 o! x
! f  y1 ^  S; M6 b$ b9 |# i职位描述
Ideal candidate will have completed BSEE , with 5 to 10 years experience in
) R& q2 e/ b: ^$ Z2 S$ cSemiconductor field.
* A2 `- W; e6 i1 S
Candidate should have strong oral and written communication skills -must be english speaking.
) L% {* E& n$ ]' t$ k
Candidate must have demonstrated strength with analog circuits, and familiarity with typical lab equipment such as scopes, DVM’s, curve tracers, and function generators. Strong bench skills are mandatory.
1 ?. ?) x% k* p5 ]* L
Ideal candidate will also have ability to debug IC’s to component level from design schematics and plots.

Failure analysis background is a plus.

( B7 T2 ^! G4 ]% g Candidate must also have ability to follow documented procedures, and must be able to work independently. Individual will report to management team in US.
1 t  F) e1 Z/ _4 s8 M' e
Job function to cover all aspects of New Product Development and Yield management,including bench-to-tester correlation, tri-temp characterization using ATE equipment, trouble shooting and yield management

ranica

高速模拟集成电路设计工程师
: r7 n" K4 h' m% b& _0 j公      司：A semiconductor company
, k4 Y( z% A) X' e8 W  B工作地点：上海
% ]" k. r% m4 R( O
. ^' q0 V* u, k8 o职位描述：  
1、负责高速模拟电路的设计、开发、优化；  
* i8 C4 W/ a2 M" y6 i- U$ ~4 u+ d. e2、版图的设计及验证；  
1 j+ `! i& q: B5 W9 O3、电路版图参数的提取及后仿真；  
4、芯片的测试和分析。

职位要求：
; O% n  _! A" U1 g% H* c5 X1）微电子、集成电路相关专业硕士或博士学位，或学士学位3年以上模拟IC设计经验；  
2）熟悉和掌握模拟集成电路及版图设计的原理与技巧；  
0 d7 ?1 `3 V' N5 }4 e# x; C% @3）有通信系统用集成电路芯片设计和成功投片经验；  
4）善于沟通、工作踏实、责任心强，具有良好的团队协作精神；  
3 L# H$ E& Q. T" j* S( W5 S5）有下述项目经验者优先：高速锁相环(PLL），时钟数据恢复电路(CDR），调制驱动电路，宽带放大器，限幅放大器，跨阻放大器等；