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發表於 2008-11-26 21:59:05
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IV. CONCLUSION
# L0 a$ [/ q% P7 ?The designs with 3-stage-inverter and 1-stage-inverter
+ s' }0 v$ y+ n r: N0 Q3 N7 g" Dcontrolling circuits have been studied to verify the optimal% ?3 f* n: x% C5 t6 g
design schemes in NMOS-based power-rail ESD clamp
( I& s4 T- r4 J9 Qcircuits. In addition, two ESD clamp NMOS transistors,
4 E/ O6 l1 C) A7 m" bhaving snapback and no snapback operations, also were codesigned
. Y* S3 u& E1 J% P& ?+ W! pwith different controlling circuits to realize the$ [% O r4 V, i0 p
impact on their required performance. According to the
) e9 a" \9 G: \- nexperiments and analyses, the 3-stage inverters can slightly
+ F7 d! F4 f, y. c* q1 oincrease the ESD robustness, but they also can dramatically
! r2 D; i* b- w9 X" ~sacrifice the mis-trigger and latch-on immunity. The 1-stage/ n8 _! U( n7 q/ H. D9 h
inverter should be an appropriate and reliable candidate for the
9 C) f4 }$ S' G% W6 w& ipower-rail ESD clamp circuits. |
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