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發表於 2008-11-20 11:53:00
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On-Chip ESD Protection for Integrated Circuits
3 X7 z* M5 G& q) N- Y/ }4 L9 N7 QAn IC Design Perspective n6 r* c4 x) U2 T; P
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by: B I. P1 H& o- m
Albert Z.H. Wang
: ~4 k) r& ]. m' f4 yIllinois Institute of Technology, Chicago, USA( M5 h- j" t( J+ Q9 n
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Dedication. ' V. m6 H/ v7 z. ^+ L+ D! N
Acknowledgements. 3 B! d! {) ~4 W. v
Preface. 1 e' z d9 m$ {0 r5 f' J
1. Introduction. 2. ESD Test Models. 3. ESD Pr
1 H* F3 S! q; v9 ^Device Solutions. 4. ESD Protection Circuit Solutions. 5. Advanced ESD Protection; Mixe
. @6 ]8 k9 ~+ h7 `. F) sand Whole-Chip ESD Protection. 6. ESD Failure Analysis and Modeling. 7. Layout and Te
* T& ^! K. C2 M! g$ G5 m7 MInfluences on ESD Protection Circuit Design. 8. ESD Simulation-Design Methodologies. 92 q) C( x6 ^' U& E! A/ i% v
Circuit Interactions. 10. Conclusion Remarks and Future Work. 4 R$ P5 ?; Q* g3 A( a- ~4 I
Appendix A: Summary fo
3 P- F2 n9 n, x. Q7 b6 o, }Standards. References.
: \' ?5 m3 K3 U; ^Appendix B: Commercial ESD Testing Systems. , w5 i! O+ b: r* P' [% Q2 Y
Appendix C: E$ E! m: p' U/ U- r9 L
Protection Circuit Design Checklist. Index. |
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