CDM ESD Protection in CMOS Integrated Circuits

semico_ljj

CDM ESD－－以前不太重视的ESD模式，现在 继HBM和MM后成为新的一种重要的ESD测试模式

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Abstract—The impacts of charged-device-model (CDM)electrostatic discharge (ESD) events on integrated circuit (IC)products are presented in this paper. The mechanism of chiplevel CDM ESD event is introduced with some case studies on CDM ESD damages. Besides the chip-level CDM ESD event, the board-level CDM ESD event, which had been reported to cause damages in many customer-returned ICs, is also investigated in this work. The chip-level and board-level CDM ESD levels of several test devices and test circuits fabricated in CMOS processes are characterized and compared. The experimental results have shown that the board-level CDM ESD level of the test circuit is much lower than the chip-level CDM ESD level, which indicates that the board-level CDM ESD test is more critical than the chip-level CDM ESD test in the field pplications.
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In addition, failure analysis reveals that the failure on the test circuit under board-level CDM ESD test is much severer than that under chip-level CDM ESD test.

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semico_ljj

“2# 大 中 小 發表於 2008-11-3 04:10 AM”，凌晨4点？？？！！！勤奋