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借鉴一下RF ESD Design in 130nm CMOS

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發表於 2008-11-1 23:05:57 | 顯示全部樓層 |閱讀模式
An ESD-Protected 5-GHz Differential Low-Noise Amplifier in a 130-nm CMOS Process+ @, N4 g6 b! x. O( f* X9 g( d& L7 k
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Abstract- A novel ESD protection design for radio-frequency (RF) differential input/output (I/O) pads is proposed and successfully
5 v$ I3 U$ y" W5 Zapplied to a 5-GHz differential low-noise amplifier (LNA) in a 130-nm CMOS process. In the proposed ESD protection design,
$ I9 ]/ Z7 Z1 r6 N7 y3 p: can ESD bus and a local ESD clamp device are added between the differential input pads to quickly bypass ESD current, especially
- b5 n4 T0 h' e+ W- f0 V3 v- l7 Junder the pin-to-pin ESD-stress condition. With 10.3-mW power consumption under 1.2-V power supply, the differential LNA: V' {3 _/ {* Q7 G4 X
with the proposed ESD protection design has the human-bodymodel (HBM) ESD robustness of 3 kV, and exhibits 18-dB power gain and 2.62-dB noise figure at 5 GHz. Experimental results have demonstrated that the proposed ESD protection circuit can be co-designed with the input matching network of LNA to simultaneously achieve excellent RF performance and high ESD robustness.
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發表於 2009-10-16 10:18:46 | 顯示全部樓層
This is what I need document....
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Thanks.
發表於 2010-2-5 14:10:00 | 顯示全部樓層
i hope u can bring me some admirations.
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