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CMOS Transistor Layout
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- g% L( B. I" `7 Q5 o* B# o4 ECopyright © 2005/ l* \+ @, m- H! D& |- [& `- q
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Table of Contents
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2 P' _% ^9 u y$ K/ ]) G! H1 x8 }Preface4 M4 \8 {$ j; ? Z8 N& Z9 v9 ~
1. Introduction .................................................................. 1
# x t" q) M) x e% |# T' d: v2. MOS Transistors ........................................................... 2
1 N$ I2 f9 M$ V }8 M3. Fabrication of MOS Transistor ..................................... 5% J8 G, @4 _0 K0 G$ ]2 Y
4. Layout a Single Transistor .......................................... 11) Q+ i5 o9 w% v3 k, @" ~
First Stroke The basic transistor layout ..................... 12
( ~ ^. n8 D! \( R5 RSecond Stroke Compact the transistor layout ................ 13
8 V9 l2 A7 h+ t. M/ N' d0 ]Third Stroke Speed up the transistor ........................... 175 r% D3 ~+ X' E
Fourth Stroke Clean up the substrate Disturbances ...... 20
m- l6 m7 n( s2 a( J4 [Fifth Stroke Balancing area, speed and noise ............ 26
7 n, h: ?2 W" H% B) }Sixth Stroke Relief the stress ...................................... 296 l5 @ p3 X2 `
Seventh Stroke Protect the gate ...................................... 30+ F7 u0 |; T Z7 ~0 S
Eighth Stroke Improve yield ..........................................32
+ K& @9 M2 U" s6 M; Z7 U- K5. Layout Several Transistors ......................................... 34
* C* q* b# O0 b/ D6 VEighth Stroke Improve yield...........................................35
' [0 s$ n% z$ k4 Y7 t- e" l5 L! D5 d3 {Re-visit# E. i5 X9 f, _' y9 j$ S% K
Ninth Stroke Close proximity .......................................361 L1 k1 d3 Y% z V7 o+ j
Tenth Stroke Interdigitated layout ............................... 366 e& o5 n5 J4 j4 j4 i0 z$ V3 h
Eleventh Stroke Dummy transistor ................................... 41
; s d! N+ k2 G" V. V9 v, a0 t1 NTwelfth Stroke Two-dimension interdigitated layout ..... 43; B' O5 L* V" d; E _% f1 S
Thirteenth Stroke Guard ring for the matched transistors ... 453 }/ d, M6 H6 V
Fourteenth Stroke Keep NMOS away from N-well ............ 45 Q: {' e, ~3 y
Fifteenth Stroke Orientate the transistor ........................... 46
- v1 U o: U' v% uSixteenth Stroke Match the interconnects ......................... 47
$ S/ n* O/ j- L, |+ u6 F- NSeventeenth Stroke The unmatchable .................................... 501 ]1 J4 j0 y/ r5 p! R8 ]& X+ k
6. Verifying the Transistor Layout ................................. 52
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: g1 V, { c. L% S! W[ 本帖最後由 semico_ljj 於 2008-11-1 04:01 PM 編輯 ] |
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