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[問題求助] 可否幫我翻譯這一段英文

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1#
發表於 2008-7-29 15:48:49 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
Dear 先進們,
小弟的英文很破,可是又非得用英文寫
希望能有好心的大師們能幫我翻譯這一段英文(論文的英文摘要)
內文如下:
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近幾年來,在高階混合性信號(mixed-signal)電路中為了能克服基底雜訊(substrate noise)與製程變異問題,通常於類比電路部份需要以對稱的方式放置,而於高雜訊數位電路需要遠離類比電路以防雜訊干擾。在佈局(floorplan)的時候,對於類比電路中的對稱區塊,我們提出一個簡單且有效的方法,把屬於同一群的區塊放置在一起且能滿足對稱限制下達到最緊密的區塊佈局。並使用基底噪音模型(substrate noise model)處理高雜訊數位區塊對於類比電路的干擾。我們使用順序對(sequence-pair)以及最長子順序對(longest common subsequence)來實現。為了得到有效的解答,我們分別對類比區塊與數位區塊進行二階段式(two-phase)佈局方法,在第一階段模擬冶煉(simulated annealing)中交互執行配置類比區塊的對稱群與非對稱群,在第二階段中處理數位區塊雜訊最小化的佈區。最後,我們和近年來的論文所提出的實驗數據比較,從數據我們證實可以得到有效的結果。
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如有人能幫忙,真的感激不盡.
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2#
發表於 2008-10-17 12:21:34 | 只看該作者
感覺如果能把原文也貼出來,一起對照這看可能效果會更好~~~~
3#
發表於 2009-12-24 18:13:51 | 只看該作者
In recent years, high-end mixed-signal (mixed-signal) circuits in the basement in order to overcome the noise (substrate noise) and process variation problems, usually part of the analog circuits need to be placed symmetrical manner, while in high-noise digital circuit need to stay away from analog circuitry to prevent noise interference. In the layout (floorplan), when the symmetry for the analog circuit blocks, we propose a simple and effective way to belong to the same group of blocks placed together and can satisfy the symmetry constraints to achieve the closest block layout. And using the noise model substrate (substrate noise model) to handle high-noise analog circuits for digital block interference. We use the order (sequence-pair), as well as the longest sub-sequence pairs (longest common subsequence) to achieve. In order to obtain an effective answer, and we were right analog blocks and digital blocks for two-stage (two-phase) layout method, in the first phase of simulation smelting (simulated annealing) in the reciprocal enforcement of configuration symmetry group of analog blocks and non - symmetry group, in the second phase of dealing with several blocks of cloth area to minimize noise. Finally, we made the papers in recent years, experimental data from the data we have proven to be effective results.
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