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//some example
( N6 R, B$ u5 b( ?# ^+ ?1 ?% A$ u! [7 [8 t8 b1 {7 M
// define variable
- \! K, J! ~5 @VARIABLE RVM1 0.077 // Metal-1 resistor / L* G; ?* X4 ` `2 T, A
VARIABLE RVM2 0.055 // Metal-2 resistor% Y Y# R( J0 U j. ^. Q0 b
VARIABLE RVM3 0.055 // Metal-3 resistor% k+ G0 l: I6 c* L
: j* ?4 z# x7 [
// lvs option
3 h8 p# e) S6 K; iLVS SPICE PREFER PINS YES0 d/ Z0 n$ q" U2 K6 W5 _
LVS ABORT ON SUPPLY ERROR NO
0 F' J8 j0 n9 ^0 ]4 PLVS ALL CAPACITOR PINS SWAPPABLE YES+ L' U+ E* y% g1 |* [
LVS RECOGNIZE GATES NONE
6 X, x: t! ^( Y3 y1 L! GLVS IGNORE PORTS NO
0 r2 K2 r5 P. i9 M+ xLVS CHECK PORT NAMES YES
3 K4 z, ^" _8 a1 k! aLVS REDUCE PARALLEL BIPOLAR YES( q! A5 |7 z; y u% g1 i! ^& r
LVS REDUCE PARALLEL MOS YES
. m: \9 b- x: ZLVS REDUCE PARALLEL DIODES YES
s0 P# m& E' NLVS REDUCE PARALLEL CAPACITORS YES/ j- n( M- @( X6 \
LVS REDUCE PARALLEL RESISTORS YES
0 J D3 V2 c, _0 r$ O0 L& nLVS REDUCE SERIES RESISTORS YES //Smashes series resistors
+ j7 Y. u+ s6 U4 QLVS REDUCE SERIES CAPACITORS YES //Smashes series capacitors( _! H# m1 J. i! b. z, s
LVS REDUCE SPLIT GATES NO //Smashes MOS split-gates.
1 F: e- K* f4 C9 y//LVS FILTER UNUSED OPTION B D E O
: s" |9 i* o! ?+ N; JLVS FILTER UNUSED OPTION AB RC RE RG7 R+ Z- D" H( W5 v* X( g. E$ r
LVS PROPERTY RESOLUTION MAXIMUM 65536 // ALL6 ^; r" Z: P" j& }6 _
. j8 N2 N+ F* e- W; }// layer definition
, p* v P6 T+ j9 a9 TLAYER DNW 1 // DNW -- Deep N-Well$ a* i( O! L) P+ w) m
LAYER NTN 11 // Native Device Blocked Implant* X! B' p$ w( G7 U, c$ z
LAYER NWELL 3 // NW -- N-Well
; }* o! P* s# T- j' }LAYER OD 8 6 7 // OD -- Thin Oxide
+ G* ?2 f3 S- R- p6 d0 P. O* D( Y( Z5 M0 O& R
// layer operation
& \: q2 s1 O+ S6 l6 B" L4 R/ yrpolywo1 = POLYG AND RHDMY 7 p& w J" X$ _$ r
rpolywo2 = rpolywo1 AND RPO
) A1 R8 u. v qdiff = OD NOT RODMY
9 r. U# W) F# U% g6 F3 arp1 = RPDMY NOT INTERACT diff ) D5 k- A. K( y. R' W) f
p1rdum = rp1 INTERACT POLYG
3 d) C6 \9 L/ v% P. z! r
& }( F6 I$ C0 T. y- b6 F, k// connect statement* R/ T) L5 [! e- c% a
CONNECT metal1 c2poly BY pl2co! J4 e$ I5 I: \ ~
CONNECT metal1 tndiff BY pl1co5 S/ x# A) S7 c+ _. T
CONNECT metal1 poly BY pl1co3 s7 B4 e3 n; A& r% V5 X
CONNECT metal1 tpdiff BY pl1co w+ N" G' |( K7 y9 Y: O6 s
CONNECT metal2 metal1 BY VIA1
2 N/ r7 H+ Q4 h' L0 G ?CONNECT metal3 metal2 BY VIA26 o& ?7 C4 C K# y2 U1 t
CONNECT metal4 metal3 BY VIA36 z& b# w1 H7 q# q
CONNECT metal5 metal4 BY VIA4
( L9 o& f5 l/ I2 c# VCONNECT metal6 metal5 BY VIA5
2 r3 E& S: O! W5 HCONNECT metal7 metal6 BY VIA6
# ]. {- l9 X8 UCONNECT metal8 metal7 BY VIA7
# ~# v. _! D. ^ G, A7 oCONNECT metal8 CTM_M7 BY CV7( X3 X+ E: F. i' K3 J. S
& {7 ?9 l/ e' M- I6 @6 j7 L3 O// device definition/ |0 O- ^$ {( J0 R
DEVICE MN(nmos) nmos poly(G) ndiff(S) ndiff(D) psub(B) [
2 K$ k) u# M0 p3 j" s property W,L: N1 h9 u: L# t9 c( S0 p3 q- z0 O
W=(perimeter_coincide(nmos, ndiff ) + perimeter_inside(nmos, ndiff)) / 2# K3 h2 p$ F- ^2 ^
L=area(nmos) / W
5 C" H( y, \7 f]
' b' O3 E U7 ^. q+ ^* C
* V5 P$ J5 N8 Z// trace property- x& l$ a' ~, m4 T
TRACE PROPERTY MN(nmos) L L 0) F6 R) B4 h' Q J
TRACE PROPERTY MN(nmos) W W 0 |
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