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發表於 2014-6-24 11:56:13
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Sr. Layout Engineer /Staff Layout Engineer3 L0 F: v# m, U7 a
" P( v2 V0 [. w# @% V公 司:one famous IC company
% w0 I: Y" D1 V9 ~2 P1 L- ^" b+ ~工作地点:上海
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Job Requirements:
5 w- N) v, q$ L' o3 ?-Work with circuit designers to build physical design floor-plan;
' l: D& _8 a9 H6 s l1 _# `-Complete the physical layout design with the constraints of circuit design requirements;
& C p, z& c; R% p5 H-Verify the physical layout design to meet both circuit design requirements and process requirements; " n9 E" ^1 T* p' \+ w. Z J' G
-Use the advanced technologies to improve layout design quality and efficiency.
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- c/ e3 |2 z; P v" R6 MQualifications:
( f; T) A0 H8 m# Z& a2 ~-College degree (or above) in Electrical Engineering or other related engineering field; 8 k/ g$ {' ?! c8 ~$ A
-At least 4 years experience in layout design field with rich tapeout experience; 0 |8 ?6 \0 c* E' x# h
-Good understanding of basic electronic principles dealing with circuit and layout design; ( r2 Y, [* W" S+ _% t' e1 r1 Z
-Familiar with IC layout methodologies, flows and CAD tools such as Cadence virtuoso layout, Caliber physical verification;
y- @ v) T7 Y7 B* r3 R2 A' X-Prefer experienced in PLL and IO design ! x' W6 l* a/ Y) k
-Patient, A good team player, Good communication skills;
- T3 h: f7 p% H) F-Can communicate with both written and spoken English. |
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