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我目前在設計一個pipeline的電路,且有防bubble機制,但在設計的過程中有些問題~1 M% b- A( g3 L& X2 a [
想請問一下大家!! Y4 P. T j& {' k/ }' K8 l
該怎麼設計?
! _5 x( Z7 d) \0 T* V以下是我需要的功能~: M4 D8 w4 q4 u7 O% [
| | | | | | | | | | | | | | | | | | | The next stage data full signal | | | | | | | | | DUT full signal to preceding stage |
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/ ~4 ~4 }' w% uThereare 5 pipe stages in our pipelining design. 4 J1 n& o# Y/ j5 ^7 @8 i. M/ q" \
It means that the input data can beobserved at the output port after 5 clock cycles. , p( z/ W1 A& a8 a; E) _5 {" K
All the stages must be readyto proceed at the same time. 7 p& s3 k5 o* G
When d_full is active, you have to keep the outputdata until d_full is disabled. ; | S! G- t# Q9 P; ^" x u. L* E
If d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data. % t& R: J/ k: ~5 k
The pipeline bubbles haveto be eliminated when d_full is active.
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